公开(公告)号：US20240355912A1

公开(公告)日：2024-10-24

申请号：US18761137

申请日：2024-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Wei-Jen CHEN ,  Pang-Chun LIU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： H01L29/66

CPC分类号： H01L29/66984

摘要： A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

公开(公告)号：US20240341200A1

公开(公告)日：2024-10-10

申请号：US18748476

申请日：2024-06-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Wei-Jen CHEN ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： H10N52/80 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

CPC分类号： H10N52/80 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

摘要： A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

公开(公告)号：US20230027792A1

公开(公告)日：2023-01-26

申请号：US17736652

申请日：2022-05-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Jih-Chao CHIU ,  Ya-Jui TSOU ,  Wei-Jen CHEN ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/08 ,  H01L43/14 ,  H01L43/06

摘要： A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

公开(公告)号：US20230397501A1

公开(公告)日：2023-12-07

申请号：US17831187

申请日：2022-06-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Jih-Chao CHIU ,  Huan-Chi SHIH ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/161 ,  G11C11/1693 ,  G11C11/1675

摘要： A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

公开(公告)号：US20230255122A1

公开(公告)日：2023-08-10

申请号：US17668514

申请日：2022-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Wei-Jen CHEN ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

CPC分类号： H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/14

摘要： A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

公开(公告)号：US20220310595A1

公开(公告)日：2022-09-29

申请号：US17839054

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Cheng-Wei LIAN

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

摘要： Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.

公开(公告)号：US20230411279A1

公开(公告)日：2023-12-21

申请号：US17845515

申请日：2022-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Liang-Hsuan PENG ,  Chih-Hung LU ,  Chih-Lin WANG ,  Song-Bor LEE

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76802 ,  H01L21/76829

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.

公开(公告)号：US20220358980A1

公开(公告)日：2022-11-10

申请号：US17871983

申请日：2022-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

摘要： A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US20220077384A1

公开(公告)日：2022-03-10

申请号：US17525927

申请日：2021-11-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

摘要： A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

公开(公告)号：US20230363287A1

公开(公告)日：2023-11-09

申请号：US18353569

申请日：2023-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

摘要： A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.