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公开(公告)号：US20210005540A1
公开(公告)日：2021-01-07
申请号：US17028843
申请日：2020-09-22
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L21/78
Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
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公开(公告)号：US09029194B2
公开(公告)日：2015-05-12
申请号：US14267565
申请日：2014-05-01
Applicant: Texas Instruments Incorporated
CPC classification number: H01L23/49575 , H01L21/56 , H01L21/565 , H01L21/82 , H01L23/3107 , H01L23/49537 , H01L23/49551 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/0401 , H01L2224/08245 , H01L2224/131 , H01L2224/16245 , H01L2224/73251 , H01L2224/80904 , H01L2224/8121 , H01L2224/81815 , H01L2224/92222 , H01L2224/97 , H01L2924/181 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/80 , H01L2224/16 , H01L2224/08 , H01L2924/00
Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
Abstract translation: 制造集成电路模块的方法从包括多个整体连接的顶部引线框架的顶部引线框条开始。 多个倒装芯片模具安装在顶部引线框架条上，每个倒装芯片的焊料凸块接合到每个顶部引线框架上的预定焊盘部分。 顶部引线框条连接到底部引线框条。 底部引线框带具有多个整体连接的底部引线框架，每个底部引线框架具有中央管芯附接焊盘（DAP）部分和外围框架部分。 每个倒装芯片模具的背面接触每个底部引线框架的DAP部分。 每个顶部引线框架的引线部分附接到每个底部引线框架的外围框架部分。 顶部引线框条附接到底部引线框条，每个倒装芯片模具的背面接触每个底部引线框架的DAP部分，并且每个顶部引线框架的引线部分连接到每个底部引线框架的外围框架部分。
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3.发明申请公开(公告)号：US20170358523A1
公开(公告)日：2017-12-14
申请号：US15688227
申请日：2017-08-28
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/56 , H01L21/78 , H01L21/48
CPC classification number: H01L23/49565 , H01L21/4842 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/49503 , H01L23/49541 , H01L23/49551 , H01L2224/97 , H01L2924/181 , H01L2924/00012
Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
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4.发明申请公开(公告)号：US20170345743A1
公开(公告)日：2017-11-30
申请号：US15680499
申请日：2017-08-18
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/56 , H01L21/78 , H01L21/48
Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
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公开(公告)号：US20150243641A1
公开(公告)日：2015-08-27
申请号：US14706052
申请日：2015-05-07
Applicant: Texas Instruments Incorporated
Inventor： Lee Han Meng@ Eugene Lee , Anis Fauzi bin Abdul Aziz , Yien Sien Khoo
IPC: H01L25/00 , H01L23/00 , H01L23/498 , H01L21/56 , H01L25/16 , H01L23/495
CPC classification number: H01L25/50 , H01L21/565 , H01L23/3107 , H01L23/49531 , H01L23/49537 , H01L23/49541 , H01L23/49568 , H01L23/49575 , H01L23/49589 , H01L23/49838 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/165 , H01L2224/0401 , H01L2224/04026 , H01L2224/06181 , H01L2224/131 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/33181 , H01L2224/8121 , H01L2224/81801 , H01L2224/81815 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/97 , H01L2924/12 , H01L2924/1306 , H01L2924/14 , H01L2924/181 , H01L2924/014 , H01L2924/00 , H01L2224/83 , H01L2224/81
Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
Abstract translation: 一种制造集成电路（IC）封装的方法，所述集成电路（IC）封装包括将裸片电连接和物理附接到插入器，将所述插入件附接到底部引线框架，将分立电路部件附接到所述插入器并将顶部引线框架附接到所述底部引线框架。
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Patent Agency Ranking
公开(公告)号：US11373940B2
公开(公告)日：2022-06-28
申请号：US17028843
申请日：2020-09-22
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L21/78
Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
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公开(公告)号：US20200091111A1
公开(公告)日：2020-03-19
申请号：US16688905
申请日：2019-11-19
Applicant: Texas Instruments Incorporated
Inventor： Lee Han Meng@ Eugene Lee , Anis Fauzi bin Abdul Aziz , Khoo Yien Sien
IPC: H01L23/00 , H01L23/495 , H01L23/498 , H01L21/78
Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.
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公开(公告)号：US09842807B2
公开(公告)日：2017-12-12
申请号：US14887047
申请日：2015-10-19
Applicant: Texas Instruments Incorporated
IPC: H01L23/538 , H01L23/495 , H01L21/768 , H01L21/56 , H01L21/48 , H01L21/78
CPC classification number: H01L23/5386 , H01L21/4853 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L23/3121 , H01L23/481 , H01L23/49503 , H01L23/4952 , H01L23/5384 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/04 , H01L2224/04026 , H01L2224/05009 , H01L2224/0579 , H01L2224/05839 , H01L2224/08245 , H01L2224/29009 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32013 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48464 , H01L2224/48465 , H01L2224/49171 , H01L2224/73251 , H01L2224/73265 , H01L2224/9222 , H01L2224/92247 , H01L2224/97 , H01L2924/35121 , H01L2924/3862 , H01L2924/00014 , H01L2224/291 , H01L2924/014 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00 , H01L2924/0781 , H01L2924/0665 , H01L2224/08 , H01L2224/80 , H01L2224/48
Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.
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公开(公告)号：US20140242755A1
公开(公告)日：2014-08-28
申请号：US14267565
申请日：2014-05-01
Applicant: Texas Instruments Incorporated
CPC classification number: H01L23/49575 , H01L21/56 , H01L21/565 , H01L21/82 , H01L23/3107 , H01L23/49537 , H01L23/49551 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/0401 , H01L2224/08245 , H01L2224/131 , H01L2224/16245 , H01L2224/73251 , H01L2224/80904 , H01L2224/8121 , H01L2224/81815 , H01L2224/92222 , H01L2224/97 , H01L2924/181 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/80 , H01L2224/16 , H01L2224/08 , H01L2924/00
Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
Abstract translation: 制造集成电路模块的方法从包括多个整体连接的顶部引线框架的顶部引线框条开始。 多个倒装芯片模具安装在顶部引线框架条上，每个倒装芯片的焊料凸块接合到每个顶部引线框架上的预定焊盘部分。 顶部引线框条连接到底部引线框条。 底部引线框带具有多个整体连接的底部引线框架，每个底部引线框架具有中央管芯附接焊盘（DAP）部分和外围框架部分。 每个倒装芯片模具的背面接触每个底部引线框架的DAP部分。 每个顶部引线框架的引线部分附接到每个底部引线框架的外围框架部分。 顶部引线框条附接到底部引线框条，每个倒装芯片模具的背面接触每个底部引线框架的DAP部分，并且每个顶部引线框架的引线部分连接到每个底部引线框架的外围框架部分。
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公开(公告)号：US10784190B2
公开(公告)日：2020-09-22
申请号：US15680499
申请日：2017-08-18
Applicant: Texas Instruments Incorporated
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L21/78
Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.
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