利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

212 条记录 (耗时 0.035 秒)

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US08183670B2

    公开(公告)日：2012-05-22

    申请号：US11651034

    申请日：2007-01-09

    申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

    发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto ,  Hiroshi Akahori ,  Keiichi Nii

    IPC分类号： H01L29/04

    CPC分类号： H01L21/3185 ,  H01L21/30604 ,  H01L21/31654 ,  H01L21/318 ,  H01L29/6659

    摘要： In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

    摘要翻译： 在形成在具有大致（110）晶面取向的硅表面上的半导体器件中，硅表面变平，使得表面Ra的算术平均偏差不大于0.15nm，优选为0.09nm，这使得能够制造 高迁移率的n-MOS晶体管。 通过在脱氧H 2 O或低OH密度气氛中清洗硅表面，通过在氧自由基气氛中重复自牺牲氧化物膜的沉积工艺和自牺牲氧化物膜的去除工艺来获得这种扁平化的硅表面 ，或通过氢或重氢强烈地终止硅表面。 自牺牲氧化膜的沉积工艺可以通过各向同性氧化进行。

    Complementary MIS device
    5.
    发明授权
    Complementary MIS device 失效
    互补MIS设备

    公开(公告)号：US07566936B2

    公开(公告)日：2009-07-28

    申请号：US11606181

    申请日：2006-11-30

    申请人： Tadahiro Ohmi ,  Koji Kotani ,  Shigetoshi Sugawa

    发明人： Tadahiro Ohmi ,  Koji Kotani ,  Shigetoshi Sugawa

    IPC分类号： H01L29/76

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/66795 ,  H01L29/7851

    摘要： A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.

    摘要翻译： CMOS器件包括具有形成在硅衬底（100）表面上并具有不同晶体表面的结构的p沟道MOS晶体管和n沟道MOS晶体管，形成在这种结构上的高质量栅极绝缘膜 通过微波等离子体处理和形成在其上的栅电极，其中上述结构的尺寸和形状被设置为使得载流子迁移率在p沟道MOS晶体管和n沟道MOS晶体管之间平衡。

    Low noise amplifier
    7.
    发明申请
    Low noise amplifier 审中-公开
    低噪声放大器

    公开(公告)号：US20070105523A1

    公开(公告)日：2007-05-10

    申请号：US10560703

    申请日：2004-06-11

    申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

    发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

    IPC分类号： H04B1/10 ,  H04B1/28 ,  H04B1/16

    CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/785 ,  H03F1/26 ,  H03F2200/372 ,  H03G1/0029 ,  H03G1/007

    摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.

    摘要翻译： 假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为 所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面，覆盖所述半导体衬底的均匀厚度的栅极绝缘体 主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及在该区域中形成的单一导电型扩散区域 半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。 这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。