公开(公告)号：US06583501B2

公开(公告)日：2003-06-24

申请号：US09499021

申请日：2000-02-07

申请人： Tai Chong Chai ,  Thiam Beng Lim ,  Yong Chua Teo ,  James Tan ,  Ray Camenforte ,  Eric Neo ,  Daniel Yap

发明人： Tai Chong Chai ,  Thiam Beng Lim ,  Yong Chua Teo ,  James Tan ,  Ray Camenforte ,  Eric Neo ,  Daniel Yap

IPC分类号： H01L23495

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

公开(公告)号：US06621151B1

公开(公告)日：2003-09-16

申请号：US09497421

申请日：2000-02-07

申请人： Tai Chong Chai ,  Thiam Beng Lim ,  Yong Chua Teo ,  James Tan ,  Raymundo Camenforte ,  Eric Neo ,  Daniel Yap

发明人： Tai Chong Chai ,  Thiam Beng Lim ,  Yong Chua Teo ,  James Tan ,  Raymundo Camenforte ,  Eric Neo ,  Daniel Yap

IPC分类号： H01L2348

CPC分类号： H01L23/49503 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead-frame for connecting and supporting an integrated circuit having an apertured frame with dimensions smaller than the corresponding dimensions of the chip so that chip-pad shoulder can be eliminated and the chip attach fillet is made remote from the chip corner.

摘要翻译： 一种用于连接和支撑集成电路的引线框架，该集成电路具有尺寸小于芯片的相应尺寸的有孔框架，使得可以消除芯片焊盘肩部并且芯片附接圆角远离芯片角落。

公开(公告)号：US5836520A

公开(公告)日：1998-11-17

申请号：US582746

申请日：1996-01-04

申请人： Sarvotham M. Bhandarkar ,  Kishore Kumar Chakravorty ,  Tai Chong Chai ,  Jian Hua Wu

发明人： Sarvotham M. Bhandarkar ,  Kishore Kumar Chakravorty ,  Tai Chong Chai ,  Jian Hua Wu

IPC分类号： H01L21/48 ,  H05K3/12 ,  H05K3/34 ,  B05B1/14

CPC分类号： H05K3/1233 ,  H01L21/4853 ,  H05K2203/0134 ,  H05K3/3478

摘要： A dispenser contains a chamber enclosed by an upper wall and a lower wall, both walls are oriented parallel to each other. The upper wall has a vertically bored inlet port and the lower wall has a plurality of vertically bored outlet ports for providing access to the chamber. The outlet ports are geometrically arranged in an array pattern characterized by equidistantly spaced rows and columns of bores. There is a plurality of baffle plates interposed between the upper wall and the lower wall. The baffle plates, which are spatially separated from each other, are oriented parallel to and spatially separated from the upper and lower walls. The baffle plates have a plurality of vertically bored holes for providing access between the inlet port and the outlet ports, whereby the dispenser is effective in providing homogeneous flow of fluid through the outlet ports.

公开(公告)号：US20060057832A1

公开(公告)日：2006-03-16

申请号：US10938239

申请日：2004-09-10

申请人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Rotaru ,  Tai Chong Chai ,  Mahadevan Iyer

发明人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Rotaru ,  Tai Chong Chai ,  Mahadevan Iyer

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/013

摘要： A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

摘要翻译： 公开了一种形成在具有接合垫的集成电路芯片上的晶片级封装及其制造方法。 晶片级封装包括至少一个第一，第二和第三分离层，其具有形成在分离层之间的至少一个第一和第二导电层。 所述至少一个第一导电层形成在所述至少一个第一分离层上并且耦合到所述粘合垫。 至少一个第二导电层形成在最后一个第二分离层上，其中至少一个第二导电层电耦合到至少一个第一导电层。 所述至少一个第三分离层允许将焊料附着到所述至少一个第二导电层，以将所述焊料电耦合到所述粘合垫。 集成电路芯片中放置有芯片接地层，用于向至少一个第一导电层和焊料提供接地。

公开(公告)号：US09506823B2

公开(公告)日：2016-11-29

申请号：US13696432

申请日：2011-05-03

申请人： Cheryl Sharmani Selvanayagam ,  Xiaowu Zhang ,  Tai Chong Chai ,  Alastair David Trigg ,  Cheng Kuo Cheng ,  Xian Tong Chen ,  Kripesh Vaidyanathan

发明人： Cheryl Sharmani Selvanayagam ,  Xiaowu Zhang ,  Tai Chong Chai ,  Alastair David Trigg ,  Cheng Kuo Cheng ,  Xian Tong Chen ,  Kripesh Vaidyanathan

IPC分类号： G01L1/22 ,  H01L21/66

CPC分类号： G01L1/22 ,  H01L22/12 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bonding stress testing arrangement and a method of determining stress are provided. The bonding stress testing arrangement includes at least one bond pad; a sensor assembly comprising any one of a first sensor arrangement, a second sensor arrangement and a combination of the first sensor arrangement and the second sensor arrangement; wherein the first sensor arrangement is adapted to measure an average stress on a portion of a bonding area under the at least one bond pad, and the second sensor arrangement is adapted to determine stress distribution over a portion or an entire of the bonding area under the at least one bond pad.

摘要翻译： 提供接合应力测试装置和确定应力的方法。 接合应力测试装置包括至少一个接合焊盘; 传感器组件，包括第一传感器布置，第二传感器布置以及第一传感器布置和第二传感器布置的组合中的任一个; 其中所述第一传感器装置适于测量所述至少一个接合焊盘下方的接合区域的一部分上的平均应力，并且所述第二传感器装置适于确定在所述至少一个接合焊盘下方的部分或整个所述接合区域的应力分布 至少一个键盘。

公开(公告)号：US20130199303A1

公开(公告)日：2013-08-08

申请号：US13696432

申请日：2011-05-03

申请人： Cheryl Sharmani Selvanayagam ,  Xiaowu Zhang ,  Tai Chong Chai ,  Alastair David Trigg ,  Cheng Kuo Cheng ,  Xian Tong Chen ,  Kripesh Vaidyanathan

发明人： Cheryl Sharmani Selvanayagam ,  Xiaowu Zhang ,  Tai Chong Chai ,  Alastair David Trigg ,  Cheng Kuo Cheng ,  Xian Tong Chen ,  Kripesh Vaidyanathan

IPC分类号： G01L1/22

CPC分类号： G01L1/22 ,  H01L22/12 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bonding stress testing arrangement and a method of determining stress are provided. The bonding stress testing arrangement includes at least one bond pad; a sensor assembly comprising any one of a first sensor arrangement, a second sensor arrangement and a combination of the first sensor arrangement and the second sensor arrangement; wherein the first sensor arrangement is adapted to measure an average stress on a portion of a bonding area under the at least one bond pad, and the second sensor arrangement is adapted to determine stress distribution over a portion or an entire of the bonding area under the at least one bond pad.

摘要翻译： 提供接合应力测试装置和确定应力的方法。 接合应力测试装置包括至少一个接合焊盘; 传感器组件，包括第一传感器布置，第二传感器布置以及第一传感器布置和第二传感器布置的组合中的任一个; 其中所述第一传感器装置适于测量所述至少一个接合焊盘下方的接合区域的一部分上的平均应力，并且所述第二传感器装置适于确定在所述至少一个接合焊盘下方的部分或整个所述接合区域的应力分布 至少一个键盘。

公开(公告)号：US20120126419A1

公开(公告)日：2012-05-24

申请号：US13055525

申请日：2008-07-24

申请人： Vaidyanathan Kripesh ,  Navas Khan Orattikalandar ,  Srinivasa Rao Vempati ,  Yak Long Samuel Lim ,  Yee Mong Khoo ,  Chee Houe Khong ,  Xiao Wu Zhang ,  Tai Chong Chai ,  Hon-Shing John Lau

发明人： Vaidyanathan Kripesh ,  Navas Khan Orattikalandar ,  Srinivasa Rao Vempati ,  Yak Long Samuel Lim ,  Yee Mong Khoo ,  Chee Houe Khong ,  Xiao Wu Zhang ,  Tai Chong Chai ,  Hon-Shing John Lau

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L29/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/161 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1624 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/35 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： According to one embodiment of the present invention, a substrate arrangement is provided. The substrate arrangement includes a first substrate; a second substrate positioned above the first substrate, the second substrate comprising a first through hole; a third substrate positioned above the second substrate, the third substrate comprising a second through hole; a first electrically conductive interconnect pillar positioned on the first substrate and extending from the first substrate through the first through hole to electrically contact the third substrate; and a second electrically conductive interconnect pillar positioned on the second substrate and extending from the second substrate through the second through hole. A method of manufacturing a substrate arrangement is also provided.

摘要翻译： 根据本发明的一个实施例，提供了一种衬底布置。 衬底布置包括第一衬底; 位于所述第一基板上方的第二基板，所述第二基板包括第一通孔; 位于所述第二基板上方的第三基板，所述第三基板包括第二通孔; 位于所述第一基板上并且从所述第一基板延伸穿过所述第一通孔的第一导电互连柱，以与所述第三基板电接触; 以及第二导电互连柱，其定位在所述第二基板上并且从所述第二基板延伸穿过所述第二通孔。 还提供了一种制造衬底布置的方法。

公开(公告)号：US07189594B2

公开(公告)日：2007-03-13

申请号：US10938239

申请日：2004-09-10

申请人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Dragos Rotaru ,  Tai Chong Chai ,  Mahadevan Krishna Iyer

发明人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Dragos Rotaru ,  Tai Chong Chai ,  Mahadevan Krishna Iyer

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/013

摘要： A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

摘要翻译： 公开了一种形成在具有接合垫的集成电路芯片上的晶片级封装及其制造方法。 晶片级封装包括至少一个第一，第二和第三分离层，其具有形成在分离层之间的至少一个第一和第二导电层。 所述至少一个第一导电层形成在所述至少一个第一分离层上并且耦合到所述粘合垫。 至少一个第二导电层形成在最后一个第二分离层上，其中至少一个第二导电层电耦合到至少一个第一导电层。 所述至少一个第三分离层允许将焊料附着到所述至少一个第二导电层，以将所述焊料电耦合到所述粘合垫。 集成电路芯片中放置有芯片接地层，用于向至少一个第一导电层和焊料提供接地。

公开(公告)号：US5967577A

公开(公告)日：1999-10-19

申请号：US146465

申请日：1998-09-03

申请人： Sarvotham M. Bhandarkar ,  Kishore Kumar Chakravorty ,  Tai Chong Chai ,  Jian Hua Wu

发明人： Sarvotham M. Bhandarkar ,  Kishore Kumar Chakravorty ,  Tai Chong Chai ,  Jian Hua Wu

IPC分类号： H01L21/48 ,  H05K3/12 ,  H05K3/34 ,  B25J15/06

CPC分类号： H05K3/1233 ,  H01L21/4853 ,  H05K2203/0134 ,  H05K3/3478

摘要： A dispenser contains a chamber enclosed by an upper wall and a lower wall, both walls are oriented parallel to each other. The upper wall has a vertically bored inlet port and the lower wall has a plurality of vertically bored outlet ports for providing access to the chamber. The outlet ports are geometrically arranged in an array pattern characterized by equidistantly spaced rows and columns of bores. There is a plurality of baffle plates interposed between the upper wall and the lower wall. The baffle plates, which are spatially separated from each other, are oriented parallel to and spatially separated from the upper and lower walls. The baffle plates have a plurality of vertically bored holes for providing access between the inlet port and the outlet ports, whereby the dispenser is effective in providing homogeneous flow of fluid through the outlet ports.

摘要翻译： 分配器包含由上壁和下壁包围的室，两个壁彼此平行取向。 上壁具有垂直钻孔的入口，并且下壁具有多个用于提供通向腔室的垂直孔的出口。 出口端口几何地布置成阵列图案，其特征在于具有等间隔的行和列的孔。 插入在上壁和下壁之间的多个挡板。 在空间上彼此分离的挡板平行于空间上与上壁和下壁分离。 挡板具有多个垂直钻孔，用于在入口和出口之间提供通路，由此分配器有效地提供通过出口的均匀流体流动。