-
Patent Agency Ranking
公开(公告)号：US10192848B2
公开(公告)日：2019-01-29
申请号：US15712680
申请日：2017-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsiun Lee , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L23/31 , H01L21/56 , H01L21/768 , H01L23/525
Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.
-
公开(公告)号：US20180350706A1
公开(公告)日：2018-12-06
申请号：US16100060
申请日：2018-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsing-Ding WANG , Chien-Hsiun Lee
IPC: H01L23/14 , H01L25/03 , H01L23/498 , H01L25/065 , H01L21/56 , H01L23/00 , H01L25/00 , H01L23/31
CPC classification number: H01L25/112 , H01L21/563 , H01L23/145 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/071 , H01L25/074 , H01L25/115 , H01L25/117 , H01L25/50 , H01L2224/131 , H01L2224/14132 , H01L2224/14165 , H01L2224/14179 , H01L2224/16225 , H01L2224/16237 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81447 , H01L2224/81815 , H01L2224/8191 , H01L2224/83385 , H01L2224/92125 , H01L2224/97 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/14 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/15331 , H01L2924/15747 , H01L2924/181 , H01L2924/18161 , H05K3/403 , H01L2924/014 , H01L2224/81 , H01L2924/00012 , H01L2924/00
Abstract: A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.
-
公开(公告)号：US10665565B2
公开(公告)日：2020-05-26
申请号：US16221986
申请日：2018-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsiun Lee , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L21/56 , H01L23/31 , H01L21/768 , H01L23/525
Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.
-
公开(公告)号：US20190123016A1
公开(公告)日：2019-04-25
申请号：US16221986
申请日：2018-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsiun Lee , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L21/768 , H01L21/56 , H01L23/31
CPC classification number: H01L24/81 , H01L21/563 , H01L21/565 , H01L21/566 , H01L21/768 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0239 , H01L2224/024 , H01L2224/0347 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05582 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/21 , H01L2224/27318 , H01L2224/27334 , H01L2224/27416 , H01L2224/2919 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83192 , H01L2224/83855 , H01L2224/92125 , H01L2224/94 , H01L2924/00014 , H01L2924/01013 , H01L2924/01047 , H01L2924/12042 , H01L2924/181 , H01L2924/2076 , H01L2224/81 , H01L2924/01029 , H01L2924/04941 , H01L2924/04953 , H01L2924/014 , H01L2224/11 , H01L2924/00
Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.
-
公开(公告)号：US20180012860A1
公开(公告)日：2018-01-11
申请号：US15712680
申请日：2017-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsiun Lee , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L23/00 , H01L21/768 , H01L23/31 , H01L21/56 , H01L23/525
CPC classification number: H01L24/81 , H01L21/563 , H01L21/565 , H01L21/566 , H01L21/768 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0239 , H01L2224/024 , H01L2224/0347 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05582 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/21 , H01L2224/27318 , H01L2224/27334 , H01L2224/27416 , H01L2224/2919 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83192 , H01L2224/83855 , H01L2224/92125 , H01L2224/94 , H01L2924/00014 , H01L2924/01013 , H01L2924/01047 , H01L2924/12042 , H01L2924/181 , H01L2924/2076 , H01L2224/81 , H01L2924/01029 , H01L2924/04941 , H01L2924/04953 , H01L2924/014 , H01L2224/11 , H01L2924/00
Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.
-
-
-
-
Search Results
5
records
(took 0.012 seconds)
