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8 条记录 (耗时 0.019 秒)

    Method for producing aromatic carboxylic acids
    2.
    发明授权
    Method for producing aromatic carboxylic acids 失效
    芳香族羧酸的制造方法

    公开(公告)号：US5663428A

    公开(公告)日：1997-09-02

    申请号：US578028

    申请日：1995-12-26

    申请人： Hideo Oikawa ,  Hiroshi Fukuhara

    发明人： Hideo Oikawa ,  Hiroshi Fukuhara

    IPC分类号： B01J31/04 ,  C07B61/00 ,  C07C51/265 ,  C07C63/26

    CPC分类号： C07C63/26 ,  C07C51/265 ,  Y02P20/52

    摘要： A method for producing aromatic carboxylic acids which comprises oxidizing a starting compound selected from the group consisting of alkyl substituted aromatic hydrocarbons and partially oxidized alkyl substituted aromatic hydrocarbons with a molecular oxygen containing gas in the presence of at least one additive selected from the group consisting of aliphatic hydrocarbons, alicyclic hydrocarbons, aliphatic alcohols, alicyclic alcohols, aldehydes, carboxylic acids and ketones and in the presence of a catalyst comprising a heavy metal compound and a bromine compound in a reaction solvent. The aliphatic alcohols, alicyclic alcohols, aldehydes, carboxylic acids and ketones have ten to thirty carbon atoms in the molecule.

    摘要翻译： 一种生产芳族羧酸的方法，包括在至少一种选自以下的添加剂的存在下，用含有分子氧的气体氧化选自烷基取代的芳族烃和部分氧化的烷基取代的芳族烃的起始化合物： 脂肪族烃，脂环族烃，脂族醇，脂环族醇，醛，羧酸和酮，并且在反应溶剂中在包含重金属化合物和溴化合物的催化剂存在下进行。 脂族醇，脂环族醇，醛，羧酸和酮在分子中具有10至30个碳原子。

    Semiconductor device and process for manufacturing the same
    4.
    发明授权
    Semiconductor device and process for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US4557036A

    公开(公告)日：1985-12-10

    申请号：US479135

    申请日：1983-03-25

    申请人： Hakaru Kyuragi ,  Hideo Oikawa

    发明人： Hakaru Kyuragi ,  Hideo Oikawa

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L21/28

    CPC分类号： H01L21/28512 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76834 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/103 ,  Y10S148/105

    摘要： A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO.sub.2 layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO.sub.2 layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO.sub.2 layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO.sub.2 layer. A semiconductor device with a high density and a high speed is realized.

    摘要翻译： 包含Si层/难熔金属氧化物层/难熔金属层的多层结构在氢气或与氢气混合的惰性气体气氛中进行退火，由此将多层结构转化为包括Si层/ 通过Si / a难熔金属层的内部氧化形成的内部SiO 2层。 内部SiO 2层仅选择性地形成在难熔金属层的表面上，因为Si从难熔金属层的一侧内部被氧化。 在MISFET的栅电极的情况下，栅电极和源电极或漏电极的接触孔经由内部SiO 2层彼此自对准。 栅极电极和源极或漏极之间的距离由内部SiO 2层的厚度决定。 实现了高密度和高速度的半导体器件。

    Method of connecting wirings through connection hole
    5.
    发明授权
    Method of connecting wirings through connection hole 失效
    通过连接孔连接布线的方法

    公开(公告)号：US5320979A

    公开(公告)日：1994-06-14

    申请号：US101780

    申请日：1993-08-03

    申请人： Chisato Hashimoto ,  Katsuyuki Machida ,  Hideo Oikawa

    发明人： Chisato Hashimoto ,  Katsuyuki Machida ,  Hideo Oikawa

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/441 ,  C23F1/00

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  Y10S438/978

    摘要： A method includes the steps of forming an insulating layer on a first conductive layer, forming a connection hole in the insulating layer, performing etching using an ion having a very low etching rate with respect to the first conductive layer and a high etching rate with respect to the insulating layer, thereby forming a taper on a side wall of the connection hole, and forming a second conductive layer on the first layer and the insulating layer. A typical example of an etching ion is an oxygen ion.

    摘要翻译： 一种方法包括以下步骤：在第一导电层上形成绝缘层，在绝缘层中形成连接孔，使用相对于第一导电层具有非常低蚀刻速率的离子进行蚀刻，并且相对于 到绝缘层，从而在连接孔的侧壁上形成锥形，并在第一层和绝缘层上形成第二导电层。 蚀刻离子的典型实例是氧离子。

    Thin film forming apparatus and method
    7.
    发明授权
    Thin film forming apparatus and method 失效
    薄膜成膜装置及方法

    公开(公告)号：US4732761A

    公开(公告)日：1988-03-22

    申请号：US842244

    申请日：1986-03-21

    申请人： Katsuyuki Machida ,  Hideo Oikawa

    发明人： Katsuyuki Machida ,  Hideo Oikawa

    IPC分类号： H01L21/205 ,  C23C14/35 ,  C23C16/40 ,  C23C16/48 ,  C23C16/511 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/768 ,  B05D5/12

    CPC分类号： C23C16/48 ,  C23C14/357 ,  C23C16/402 ,  C23C16/511 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76819

    摘要： An apparatus for forming a thin film to planarize a surface of a semiconductor device having convex and concave regions, comprising a plasma generating chamber into which are an Ar gas and an O.sub.2 gas are supplied so that a plasma is produced; a specimen chamber in which a substrate electrode upon which a specimen substrate is placed and which is in partial communication with the plasma generating chamber and into which an SiH.sub.4 gas as a film material is introduced; and a bias power source for applying a bias voltage to the substrate electrode so that ions sufficiently impinge substantially vertically upon the electrode to perform ion etching. First, an SiO.sub.2 film is deposited on the specimen substrate by using the O.sub.2 and SiH.sub.4 gases. In the next step, Ar plasma and O.sub.2 plasma are produced in the plasma generating chamber and a bias voltage is applied to the substrate electrode. As a result, deposition and etching occur simultaneously, whereby the surface of the device having convex and concave regions is planarized with an SiO.sub.2 film. Submicron interconnections can be planarized with easily setting planarization conditions at a low rf power. The planarization time can be shortened.

    摘要翻译： 一种用于形成薄膜以平坦化具有凸和凹区域的半导体器件的表面的装置，包括其中供给有Ar气体和O 2气体的等离子体产生室，从而产生等离子体; 试样室，其中放置有试样基板并与等离子体发生室部分连通的基板电极，并且引入作为膜材料的SiH 4气体; 以及偏置电源，用于向衬底电极施加偏置电压，使得离子充分地基本垂直地撞击在电极上以进行离子蚀刻。 首先，使用O 2和SiH 4气体在样品基板上沉积SiO 2膜。 在下一步骤中，在等离子体发生室中产生Ar等离子体和O 2等离子体，并且将偏置电压施加到衬底电极。 结果，沉积和蚀刻同时发生，由此具有凸区域的器件的表面被SiO 2膜平坦化。 亚微米互连可以平坦化，容易设置低功率的平坦化条件。 可以缩短平坦化时间。