公开(公告)号：US5184204A

公开(公告)日：1993-02-02

申请号：US645872

申请日：1991-01-24

申请人： Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Masakatsu Hoshi ,  Yutaka Enokido ,  Yukitsugu Hirota

发明人： Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Masakatsu Hoshi ,  Yutaka Enokido ,  Yukitsugu Hirota

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/0878

摘要： A semiconductor device in which the breakdown voltages of the cell unit and the guard ring can easily be matched, and the surge endurance of the device can be improved. This semiconductor device includes a guard ring region surrounding the cell diffusion layers which is formed from an array of a plurality of guard ring cells, where each of the guard ring cells is identical to each of the cell diffusion layers and the guard ring cells are electrically connected mutually, so that the diffusion depths of each of the cells of the guard ring region and the cell diffusion layers are identical, and consequently the breakdown voltages for the guard ring region and the cell diffusion layers can be made equal to each other.

摘要翻译： 可以容易地匹配电池单元和保护环的击穿电压的半导体器件，并且可以提高器件的浪涌耐久性。 该半导体器件包括围绕由多个保护环电池的阵列形成的电池扩散层的保护环区域，其中每个保护环电池与每个电池扩散层相同，保护环电池为电 相互连接，使得保护环区域和电池扩散层的每个电池的扩散深度相同，因此保护环区域和电池扩散层的击穿电压可以彼此相等。

公开(公告)号：US5192989A

公开(公告)日：1993-03-09

申请号：US618358

申请日：1990-11-27

申请人： Tsutomu Matsushita ,  Teruyoshi Mihara ,  Masakatsu Hoshi ,  Kenji Yao

发明人： Tsutomu Matsushita ,  Teruyoshi Mihara ,  Masakatsu Hoshi ,  Kenji Yao

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/7801 ,  H01L29/0696 ,  H01L29/41758

摘要： A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.

摘要翻译： 具有导通电阻小的横向DMOS FET器件。 该装置包括由多个单元电池形成的单元结构，每个单位单元包括：形成在第一导电类型的基板的一侧的第一导电类型的源区; 形成在源极区周围的第二导电类型的沟道区; 以及位于所述沟道区周围的多个第一导电类型的漏极接触区域; 以及源电极，栅极电极和漏电极，所有这些都形成在基板的相同的一侧上。 或者，每个单电池可以包括：形成在第一导电类型的衬底的一侧上的第一导电类型的漏极接触区域; 形成在所述漏极接触区域周围的第二导电类型的沟道区域; 以及位于沟道区周围的多个第一导电类型的源极区。

公开(公告)号：US4893158A

公开(公告)日：1990-01-09

申请号：US209237

申请日：1988-06-20

申请人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

发明人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03K17/082

CPC分类号： H01L29/7815 ,  H01L27/0251 ,  H01L27/0623 ,  H03K17/0822 ,  H01L2924/0002

摘要： A power MOSFET is provided with a protective circuit including a monitor MOSFET whose drain is connected with the drain of the power MOSFET, a monitor resistor connected betwen the sources of the power and monitor MOSFETs, and a monitor transistor for decreasing a gate voltage of the power MOSFET when a voltage across the monitor resistor exceeds a predetermined level representing a dangerous condition of the device.

摘要翻译： 功率MOSFET具有保护电路，该保护电路包括监控MOSFET，漏极与功率MOSFET的漏极连接，监控电阻连接在电源和监视器MOSFET的源极之间，监视晶体管用于降低栅极电压 当监视器电阻两端的电压超过表示设备的危险状况的预定电平时，功率MOSFET。

公开(公告)号：US5040034A

公开(公告)日：1991-08-13

申请号：US465748

申请日：1990-01-18

申请人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

发明人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/7839 ,  Y10S257/902

摘要： A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.

摘要翻译： 半导体器件包括作为漏极区域的半导体衬底。 金属源区位于基板的第一表面上。 金属和衬底构成肖特基结。 包括栅电极和围绕栅电极的绝缘膜的绝缘栅极与肖特基结相邻，使得由肖特基结和衬底中的绝缘栅极形成的角度是锐角。 肖特基金属的一部分可以以衬底的形式被埋入，并且可以在绝缘栅极附近的柱上形成肖特基结的沟道区。

公开(公告)号：US5049953A

公开(公告)日：1991-09-17

申请号：US465750

申请日：1990-01-18

申请人： Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

发明人： Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/48 ,  H01L27/02 ,  H01L29/10 ,  H01L29/34

CPC分类号： H01L29/7839 ,  Y10S257/902

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.

摘要翻译： 半导体器件包括：第一导电类型的半导体衬底，其中在衬底中形成漏极区，并且通过形成在其上的绝缘膜在衬底的表面上形成栅电极。 作为源极区域的肖特金属金属在远离漏极区域的肖特基金属和衬底的与栅极电极附近的界面处构成肖特基结的表面上形成。 第二导电类型的屏蔽层介于除了肖特基结之外的肖特基金属和基板之间。 栅电极控制肖特基结的隧道电流。

公开(公告)号：US4937639A

公开(公告)日：1990-06-26

申请号：US257577

申请日：1988-10-14

申请人： Kenji Yao ,  Teruyoshi Mihara ,  Noriyuki Abe ,  Tsutomu Matsushita

发明人： Kenji Yao ,  Teruyoshi Mihara ,  Noriyuki Abe ,  Tsutomu Matsushita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/08 ,  H01L27/092 ,  H01L27/118

CPC分类号： H01L27/0251 ,  H01L27/0921 ,  H01L27/11898

摘要： An input protector device for a semiconductor device such as a CMOS device, in which a first resistor is formed on an insulating film of a semiconductor substrate, and a second resistor is formed of an impurity diffusion region in the substrate, the first and second resistors and a capacitor being coupled to one another in series to constitute a filter circuit, and in which first and second diodes each cooperated with at least one of the first and second resistors, by-passing noises having low and high voltages, respectively, and a high frequency noise is cut by the filter circuit, thereby effectively preventing latchup.

公开(公告)号：US4972240A

公开(公告)日：1990-11-20

申请号：US318569

申请日：1989-03-03

申请人： Koichi Murakami ,  Teruyoshi Mihara ,  Yukitsugu Hirota

发明人： Koichi Murakami ,  Teruyoshi Mihara ,  Yukitsugu Hirota

IPC分类号： H01L29/41 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41 ,  H01L29/41741

摘要： A vertical power MOS transistor, in which a gate oxide film is formed over partial areas of a semiconductor substrate having a first conductivity type, which functions as a drain, a channel region having a second conductivity type formed in the substrate, and a source region having the first conductivity type, formed in the channel region, and a gate electrode is formed on the gate oxide film, in which an insulating film covers the gate electrode, and a source electrode is formed on the insulating film, and in which an ohmic contact electrode is formed on portions of a source region an a channel region, and a coupling member connects the ohmic contact electrode with the source electrode to separate the source electrode from the gate electrode edge portion.

摘要翻译： 一种垂直功率MOS晶体管，其中在作为漏极的第一导电类型的半导体衬底的部分区域上形成栅氧化膜，在衬底中形成具有第二导电类型的沟道区，以及源极区 具有形成在沟道区中的第一导电类型，并且在绝缘膜覆盖栅电极的栅氧化膜上形成栅电极，并且在绝缘膜上形成源电极，其中欧姆 接触电极形成在源极区域的沟道区域的部分上，并且耦合构件将欧姆接触电极与源极电极连接，以将源极电极与栅电极边缘部分分离。

公开(公告)号：US5629704A

公开(公告)日：1997-05-13

申请号：US527677

申请日：1995-09-12

申请人： Kraisorn Throngnumchai ,  Teruyoshi Mihara ,  Hiroshige Fukuhara ,  Yukitsugu Hirota

发明人： Kraisorn Throngnumchai ,  Teruyoshi Mihara ,  Hiroshige Fukuhara ,  Yukitsugu Hirota

IPC分类号： H01L31/10 ,  G01S7/02 ,  G01S7/48 ,  G01S7/523 ,  G01S13/10 ,  G01S13/46 ,  G01S13/93 ,  G01S15/10 ,  G01S15/46 ,  G01S15/93 ,  G01S17/10 ,  G01S17/46 ,  G01S17/93 ,  H01L31/00 ,  G01S7/483

CPC分类号： G01S17/46 ,  G01S7/4914 ,  G01S13/46 ,  G01S15/46

摘要： In a radar target position detecting apparatus, beams (, for example, light beams) irradiated from a transmitter(, for example, LED) have a predetermined divergence angle, a plurality of light (beam) receiving elements such as photodiode arrays each having a different receiving angle (directivity) are arranged in an array form, and a direction of a reflected wave (beam) is identified according to a position of the arrayed beam (wave) receiving elements in the array at which the reflected wave (beam) is captured.

摘要翻译： 在雷达目标位置检测装置中，从发射器（例如，LED）照射的光束（例如，光束）具有预定的发散角，多个光（光束）接收元件，例如光电二极管阵列，每个具有 以阵列形式布置不同的接收角（方向性），并且根据反射波（波束）的阵列中的阵列波束（波）接收元件的位置来识别反射波（波束）的方向 被捕获。

公开(公告)号：US5635742A

公开(公告)日：1997-06-03

申请号：US660211

申请日：1996-06-03

申请人： Masakatsu Hoshi ,  Teruyoshi Mihara

发明人： Masakatsu Hoshi ,  Teruyoshi Mihara

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L27/10

CPC分类号： H01L29/0696 ,  H01L29/41741 ,  H01L29/7809 ,  H01L29/41766 ,  H01L29/456

摘要： A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

摘要翻译： 横向双扩散MOSFET具有半导体基板，形成在基板上的漏极区域，形成在漏极区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，通过栅电极形成的源极和漏极开口， 形成在漏极区域下方的第一导电区域，形成在源极开口上的源极电极，形成在漏极开口上的漏电极，以及用于将漏电极连接到第一导电区域的第二导电区域。 源极和漏极开口循环布置，使得至少两排源极开口布置在相邻的漏极开口之间，以降低MOSFET的导通电阻。

公开(公告)号：US07217950B2

公开(公告)日：2007-05-15

申请号：US10682154

申请日：2003-10-10

申请人： Saichirou Kaneko ,  Masakatsu Hoshi ,  Kraisorn Throngnumchai ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Teruyoshi Mihara

发明人： Saichirou Kaneko ,  Masakatsu Hoshi ,  Kraisorn Throngnumchai ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Teruyoshi Mihara

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/772 ,  H01L29/7813 ,  H01L29/7828

摘要： The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.

摘要翻译： 本发明提供了一种隧道注入装置，其包括由第一半导体制成的接收层，由具有窄于第一半导体带隙的第二半导体制成的阻挡层形成层与接收层冶金接触 设置在阻挡层形成层上的栅极绝缘膜。 栅电极控制在接收层和阻挡层形成层之间的异质结界面处产生的势垒的宽度，以便改变载流子穿过屏障的隧穿概率。 该装置还包括与接收层接触的载体接收区域和与阻挡层形成层接触的载体供给区域。