公开(公告)号：US5629704A

公开(公告)日：1997-05-13

申请号：US527677

申请日：1995-09-12

申请人： Kraisorn Throngnumchai ,  Teruyoshi Mihara ,  Hiroshige Fukuhara ,  Yukitsugu Hirota

发明人： Kraisorn Throngnumchai ,  Teruyoshi Mihara ,  Hiroshige Fukuhara ,  Yukitsugu Hirota

IPC分类号： H01L31/10 ,  G01S7/02 ,  G01S7/48 ,  G01S7/523 ,  G01S13/10 ,  G01S13/46 ,  G01S13/93 ,  G01S15/10 ,  G01S15/46 ,  G01S15/93 ,  G01S17/10 ,  G01S17/46 ,  G01S17/93 ,  H01L31/00 ,  G01S7/483

CPC分类号： G01S17/46 ,  G01S7/4914 ,  G01S13/46 ,  G01S15/46

摘要： In a radar target position detecting apparatus, beams (, for example, light beams) irradiated from a transmitter(, for example, LED) have a predetermined divergence angle, a plurality of light (beam) receiving elements such as photodiode arrays each having a different receiving angle (directivity) are arranged in an array form, and a direction of a reflected wave (beam) is identified according to a position of the arrayed beam (wave) receiving elements in the array at which the reflected wave (beam) is captured.

摘要翻译： 在雷达目标位置检测装置中，从发射器（例如，LED）照射的光束（例如，光束）具有预定的发散角，多个光（光束）接收元件，例如光电二极管阵列，每个具有 以阵列形式布置不同的接收角（方向性），并且根据反射波（波束）的阵列中的阵列波束（波）接收元件的位置来识别反射波（波束）的方向 被捕获。

公开(公告)号：US07217950B2

公开(公告)日：2007-05-15

申请号：US10682154

申请日：2003-10-10

申请人： Saichirou Kaneko ,  Masakatsu Hoshi ,  Kraisorn Throngnumchai ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Teruyoshi Mihara

发明人： Saichirou Kaneko ,  Masakatsu Hoshi ,  Kraisorn Throngnumchai ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Teruyoshi Mihara

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/772 ,  H01L29/7813 ,  H01L29/7828

摘要： The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.

摘要翻译： 本发明提供了一种隧道注入装置，其包括由第一半导体制成的接收层，由具有窄于第一半导体带隙的第二半导体制成的阻挡层形成层与接收层冶金接触 设置在阻挡层形成层上的栅极绝缘膜。 栅电极控制在接收层和阻挡层形成层之间的异质结界面处产生的势垒的宽度，以便改变载流子穿过屏障的隧穿概率。 该装置还包括与接收层接触的载体接收区域和与阻挡层形成层接触的载体供给区域。

公开(公告)号：US5675169A

公开(公告)日：1997-10-07

申请号：US451750

申请日：1995-05-26

申请人： Masakatsu Hoshi ,  Teruyoshi Mihara ,  Kraisorn Throngnumchai

发明人： Masakatsu Hoshi ,  Teruyoshi Mihara ,  Kraisorn Throngnumchai

IPC分类号： H02P7/29 ,  H01L27/02 ,  H02P7/00 ,  H03K17/082 ,  H03K17/687 ,  H03K17/695 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94 ,  H02H5/04

CPC分类号： H01L27/0251 ,  H02P7/04 ,  H03K17/0822 ,  H03K17/6871 ,  H01L2924/0002

摘要： A semiconductor device having a surge input detecting circuit is provided with the driving circuit for, for example, reversible motor. To prevent MOS power transistors constituting the power driving circuit from their destructive breakdowns (failures), when the surge input detecting circuit block detects the surge voltage input through the driving circuit which exceeds a predetermined voltage, namely, a maximum rated power supply voltage of the power driving circuit, the surge input detecting circuit outputs the signal to turn the MOS power transistors in off-states. These circuit elements are integrally mounted on a semiconductor chip. The surge input detecting circuit block detects such a surge input through a power supply terminal in terms of either of its voltage, its current, or the temperature rise in the semiconductor chip. The breakdown voltage per power transistor can be half the maximum rated power supply voltage. In addition, the surge input detecting circuit block and these power MOS transistors are fabricated into the same semiconductor chip.

摘要翻译： 具有浪涌输入检测电路的半导体器件设置有用于例如可逆电动机的驱动电路。 为了防止构成电力驱动电路的MOS功率晶体管的破坏性故障（故障），当浪涌输入检测电路块检测到通过驱动电路输入的浪涌电压超过预定电压时，即最大额定电源电压 电源驱动电路，浪涌输入检测电路输出该信号，使MOS功率晶体管处于断开状态。 这些电路元件一体地安装在半导体芯片上。 浪涌输入​​检测电路块根据其电压，电流或半导体芯片的温度升高来检测通过电源端子的浪涌输入。 每个功率晶体管的击穿电压可以是最大额定电源电压的一半。 此外，浪涌输入检测电路块和这些功率MOS晶体管被制造成相同的半导体芯片。

公开(公告)号：US4893158A

公开(公告)日：1990-01-09

申请号：US209237

申请日：1988-06-20

申请人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

发明人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03K17/082

CPC分类号： H01L29/7815 ,  H01L27/0251 ,  H01L27/0623 ,  H03K17/0822 ,  H01L2924/0002

摘要： A power MOSFET is provided with a protective circuit including a monitor MOSFET whose drain is connected with the drain of the power MOSFET, a monitor resistor connected betwen the sources of the power and monitor MOSFETs, and a monitor transistor for decreasing a gate voltage of the power MOSFET when a voltage across the monitor resistor exceeds a predetermined level representing a dangerous condition of the device.

摘要翻译： 功率MOSFET具有保护电路，该保护电路包括监控MOSFET，漏极与功率MOSFET的漏极连接，监控电阻连接在电源和监视器MOSFET的源极之间，监视晶体管用于降低栅极电压 当监视器电阻两端的电压超过表示设备的危险状况的预定电平时，功率MOSFET。

公开(公告)号：US5184204A

公开(公告)日：1993-02-02

申请号：US645872

申请日：1991-01-24

申请人： Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Masakatsu Hoshi ,  Yutaka Enokido ,  Yukitsugu Hirota

发明人： Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Masakatsu Hoshi ,  Yutaka Enokido ,  Yukitsugu Hirota

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/0878

摘要： A semiconductor device in which the breakdown voltages of the cell unit and the guard ring can easily be matched, and the surge endurance of the device can be improved. This semiconductor device includes a guard ring region surrounding the cell diffusion layers which is formed from an array of a plurality of guard ring cells, where each of the guard ring cells is identical to each of the cell diffusion layers and the guard ring cells are electrically connected mutually, so that the diffusion depths of each of the cells of the guard ring region and the cell diffusion layers are identical, and consequently the breakdown voltages for the guard ring region and the cell diffusion layers can be made equal to each other.

摘要翻译： 可以容易地匹配电池单元和保护环的击穿电压的半导体器件，并且可以提高器件的浪涌耐久性。 该半导体器件包括围绕由多个保护环电池的阵列形成的电池扩散层的保护环区域，其中每个保护环电池与每个电池扩散层相同，保护环电池为电 相互连接，使得保护环区域和电池扩散层的每个电池的扩散深度相同，因此保护环区域和电池扩散层的击穿电压可以彼此相等。

公开(公告)号：US4972240A

公开(公告)日：1990-11-20

申请号：US318569

申请日：1989-03-03

申请人： Koichi Murakami ,  Teruyoshi Mihara ,  Yukitsugu Hirota

发明人： Koichi Murakami ,  Teruyoshi Mihara ,  Yukitsugu Hirota

IPC分类号： H01L29/41 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41 ,  H01L29/41741

摘要： A vertical power MOS transistor, in which a gate oxide film is formed over partial areas of a semiconductor substrate having a first conductivity type, which functions as a drain, a channel region having a second conductivity type formed in the substrate, and a source region having the first conductivity type, formed in the channel region, and a gate electrode is formed on the gate oxide film, in which an insulating film covers the gate electrode, and a source electrode is formed on the insulating film, and in which an ohmic contact electrode is formed on portions of a source region an a channel region, and a coupling member connects the ohmic contact electrode with the source electrode to separate the source electrode from the gate electrode edge portion.

摘要翻译： 一种垂直功率MOS晶体管，其中在作为漏极的第一导电类型的半导体衬底的部分区域上形成栅氧化膜，在衬底中形成具有第二导电类型的沟道区，以及源极区 具有形成在沟道区中的第一导电类型，并且在绝缘膜覆盖栅电极的栅氧化膜上形成栅电极，并且在绝缘膜上形成源电极，其中欧姆 接触电极形成在源极区域的沟道区域的部分上，并且耦合构件将欧姆接触电极与源极电极连接，以将源极电极与栅电极边缘部分分离。

公开(公告)号：US5635742A

公开(公告)日：1997-06-03

申请号：US660211

申请日：1996-06-03

申请人： Masakatsu Hoshi ,  Teruyoshi Mihara

发明人： Masakatsu Hoshi ,  Teruyoshi Mihara

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L27/10

CPC分类号： H01L29/0696 ,  H01L29/41741 ,  H01L29/7809 ,  H01L29/41766 ,  H01L29/456

摘要： A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

摘要翻译： 横向双扩散MOSFET具有半导体基板，形成在基板上的漏极区域，形成在漏极区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，通过栅电极形成的源极和漏极开口， 形成在漏极区域下方的第一导电区域，形成在源极开口上的源极电极，形成在漏极开口上的漏电极，以及用于将漏电极连接到第一导电区域的第二导电区域。 源极和漏极开口循环布置，使得至少两排源极开口布置在相邻的漏极开口之间，以降低MOSFET的导通电阻。

公开(公告)号：USRE35405E

公开(公告)日：1996-12-17

申请号：US288731

申请日：1994-08-12

申请人： Yoshinori Murakami ,  Teruyoshi Mihara

发明人： Yoshinori Murakami ,  Teruyoshi Mihara

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/66416 ,  H01L29/66666 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/05

摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

摘要翻译： 一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁 邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

公开(公告)号：US4931846A

公开(公告)日：1990-06-05

申请号：US185387

申请日：1988-04-25

申请人： Teruyoshi Mihara

发明人： Teruyoshi Mihara

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/1095 ,  H01L29/0626 ,  H01L29/0878

摘要： A vertical MOSFET device has a first conductivity type substrate layer serving as a drain, a second conductivity type channel region extending into said substrate layer from a top surface, and a first conductivity type source region extending into the channel region from the top surface. The channel region has a peripheral subregion extending deeply into the substrate layer from the top surface under an insulated gate electrode, and a shallow central subregion shallower than the peripheral subregion. There is further provided a second conductivity type underlying layer formed under the shallow central subregion so as to form a voltage regulating diode with the channel region at a position shallower than the bottom of the peripheral subregion.

公开(公告)号：US4862233A

公开(公告)日：1989-08-29

申请号：US63116

申请日：1987-06-17

申请人： Tsutomu Matsushita ,  Teruyoshi Mihara

发明人： Tsutomu Matsushita ,  Teruyoshi Mihara

IPC分类号： H01L27/08 ,  H01L21/76 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/7802

摘要： Vertical MOS and another component such as CMOS are made in a single semiconductor substrate having a highly doped underlying layer and a lightly doped epitaxial surface layer of a first conductivity type. The vertical MOS includes a channel region of a second conductivity type, formed in the surface layer, and a source region of the first conductivity type, formed in the channel region. The channel region is made deep and joined with the highly doped underlying layer to form a first Zener diode for regulating a drain-source voltage. A drain electrode is formed on the bottom surface of the substrate and connected to a power supply, and a topside source electrode is connected to a load. The vertical MOS is surrounded, and separated from the CMOS, by a grounded guard ring region of the second conductivity type, formed in the surface layer. The guard ring region is also made deep and joined with the underlying layer.

摘要翻译： 垂直MOS和诸如CMOS的另一部件在具有高掺杂的下层和具有第一导电类型的轻掺杂外延表面层的单个半导体衬底中制成。 垂直MOS包括形成在表面层中的第二导电类型的沟道区域和形成在沟道区域中的第一导电类型的源极区域。 沟道区域被制成深并与高度掺杂的下层连接，以形成用于调节漏极 - 源极电压的第一齐纳二极管。 漏极电极形成在基板的底面上，与电源连接，顶侧的源电极与负载连接。 垂直MOS通过形成在表面层中的第二导电类型的接地保护环区域被包围并与CMOS分离。 保护环区域也是深层的，并与底层相连。