专利检索 ap:("Thomas E. Grebs" OR "Nathan Lawrence Kraft" OR "Rodney Ridley" OR "Gary M. Dolny" OR "Joseph A. Yedinak" OR "Christopher Boguslaw Kocon" OR "Ashok Challa") AND inv:"Rodney Ridley" 第 1 页

1.

发明授权
Shielded gate field effect transistors 有权
标题翻译：屏蔽栅场效应晶体管

公开(公告)号：US08803207B2

公开(公告)日：2014-08-12

申请号：US13081400

申请日：2011-04-06

申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

IPC分类号： H01L29/76 , H01L29/66

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

摘要翻译： 在一个一般方面，一种装置可以包括设置在半导体区域中的沟槽，衬在沟槽的侧壁的下部的屏蔽电介质层和沟槽的底表面，以及衬在该侧壁的上部的栅极电介质的沟槽。该设备还可以包括设置在沟槽的下部并由屏蔽电介质层与半导体区域绝缘的屏蔽电极，以及设置在屏蔽电极上的沟槽中的电极间电介质（IED），其中屏蔽电极具有一个弯曲的顶面。

2.

发明申请
Method for Forming Shielded Gate Field Effect Transistors 有权
标题翻译：屏蔽栅场效应晶体管形成方法

公开(公告)号：US20110212586A1

公开(公告)日：2011-09-01

申请号：US13081400

申请日：2011-04-06

申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

IPC分类号： H01L21/336 , H01L21/3205

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED.

摘要翻译： 用于形成场效应晶体管的方法包括在半导体区域中形成沟槽，并形成衬在沟槽的下侧壁和底表面的电介质层。在形成电介质层之后，沟槽的下部填充有屏蔽电极。通过进行蒸汽环境氧化并进行干燥环境氧化，在屏蔽电极上的沟槽中形成电极间电介质（IED）。栅电极形成在沟槽的上部。栅电极可以通过IED与屏蔽电极绝缘。

3.

发明申请
Method for Forming Shielded Gate Field Effect Transistor Using Spacers 有权
标题翻译：用隔板形成屏蔽栅场效应晶体管的方法

公开(公告)号：US20090111231A1

公开(公告)日：2009-04-30

申请号：US12344859

申请日：2008-12-29

申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

摘要翻译： 在半导体区域中形成沟槽。形成在沟槽的侧壁和底表面上的介电层。电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。在形成电介质层之后，沟槽的下部填充有屏蔽电极。电介质间隔物沿着上沟槽侧壁形成。在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。在形成IED之后，去除电介质间隔物。

4.

发明授权
Methods for forming shielded gate field effect transistors 有权
标题翻译：形成屏蔽栅场效应晶体管的方法

公开(公告)号：US07476589B2

公开(公告)日：2009-01-13

申请号：US11479117

申请日：2006-06-29

申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley

发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley

IPC分类号： H01L21/336 , H01L21/4763

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

摘要翻译： 场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

5.

发明授权
Method for forming shielded gate field effect transistor using spacers 有权
标题翻译：用间隔物形成屏蔽栅场效应晶体管的方法

公开(公告)号：US07935577B2

公开(公告)日：2011-05-03

申请号：US12344859

申请日：2008-12-29

申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley

发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley

IPC分类号： H01L21/8232 , H01L21/84 , H01L21/00 , H01L21/336

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

摘要翻译： 在半导体区域中形成沟槽。形成在沟槽的侧壁和底表面上的介电层。电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。在形成电介质层之后，沟槽的下部填充有屏蔽电极。电介质间隔物沿着上沟槽侧壁形成。在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。在形成IED之后，去除电介质间隔物。

6.

发明申请
Structures and methods for forming shielded gate field effect transistors 有权
标题翻译：用于形成屏蔽栅场效应晶体管的结构和方法

公开(公告)号：US20070032020A1

公开(公告)日：2007-02-08

申请号：US11479117

申请日：2006-06-29

申请人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa

发明人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa

IPC分类号： H01L21/336 , H01L21/3205

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811

摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

摘要翻译： 场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

7.

发明申请
Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法

公开(公告)号：US20050167742A1

公开(公告)日：2005-08-04

申请号：US11026276

申请日：2004-12-29

申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey

发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey

IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335

CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014

摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

摘要翻译： 公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

8.

发明申请
Trench FET with Improved Body to Gate Alignment 有权
标题翻译：具有改进的阀门对准的沟槽FET

公开(公告)号：US20070082441A1

公开(公告)日：2007-04-12

申请号：US11551992

申请日：2006-10-23

申请人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny

发明人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/13055 , H01L2924/13091 , H01L2924/00

摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

摘要翻译： 场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。每个沟槽部分地填充有一种或多种材料。执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。然后在每个身体区域中形成第一导电类型的源区域。