公开(公告)号：US4933737A

公开(公告)日：1990-06-12

申请号：US56127

申请日：1987-06-01

申请人： Tohru Nakamura ,  Takao Miyazaki ,  Susumu Takahashi ,  Ichiro Imaizumi ,  Takahiro Okabe ,  Minoru Nagata ,  Masao Kawamura

发明人： Tohru Nakamura ,  Takao Miyazaki ,  Susumu Takahashi ,  Ichiro Imaizumi ,  Takahiro Okabe ,  Minoru Nagata ,  Masao Kawamura

IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8226 ,  H01L23/532 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/73

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/28525 ,  H01L23/53271 ,  H01L27/0233 ,  H01L27/06 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/7317 ,  H01L2924/0002 ,  Y10S438/965

摘要： A bipolar transistor comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinsic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

摘要翻译： 双极晶体管包括具有凸部的n型Si半导体本体，覆盖半导体主体的除凸部以外的表面的绝缘膜以及形成在绝缘膜上的p型多晶Si层。 形成在凸部中的p型区域作为本征基极区域，多晶Si层用作非本征基极区域，在本征基极区域中形成的n型区域用作发射极区域，并且主体用作 一个收集区域。

公开(公告)号：US5019523A

公开(公告)日：1991-05-28

申请号：US501964

申请日：1990-03-30

申请人： Tohru Nakamura ,  Takao Miyazaki ,  Susumu Takahashi ,  Ichiro Imaizumi ,  Takahiro Okabe ,  Minoru Nagata ,  Masao Kawamura

发明人： Tohru Nakamura ,  Takao Miyazaki ,  Susumu Takahashi ,  Ichiro Imaizumi ,  Takahiro Okabe ,  Minoru Nagata ,  Masao Kawamura

IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8226 ,  H01L23/532 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/73

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/28525 ,  H01L23/53271 ,  H01L27/0233 ,  H01L27/06 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/7317 ,  H01L2924/0002 ,  Y10S438/965

摘要： Disclosed is a process for making a bipolar transistor which comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

公开(公告)号：US4825281A

公开(公告)日：1989-04-25

申请号：US435552

申请日：1982-10-21

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/331 ,  H01L27/06 ,  H01L29/423 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L23/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L29/42304 ,  H01L29/72 ,  H01L29/732 ,  H01L29/735

摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

摘要翻译： 一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面 的绝缘膜基本上均匀。

公开(公告)号：US5061645A

公开(公告)日：1991-10-29

申请号：US498489

申请日：1990-03-26

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/331 ,  H01L27/06 ,  H01L29/423 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L29/42304 ,  H01L29/72 ,  H01L29/732 ,  H01L29/735

摘要： A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

公开(公告)号：US4258379A

公开(公告)日：1981-03-24

申请号：US78452

申请日：1979-09-24

申请人： Tomoyuki Watanabe ,  Takahiro Okabe ,  Minoru Nagata ,  Tohru Nakamura ,  Kenji Kaneko ,  Yutaka Okada ,  Norio Anzai ,  Takanori Nishimura ,  Takashi Agatsuma

发明人： Tomoyuki Watanabe ,  Takahiro Okabe ,  Minoru Nagata ,  Tohru Nakamura ,  Kenji Kaneko ,  Yutaka Okada ,  Norio Anzai ,  Takanori Nishimura ,  Takashi Agatsuma

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H03K19/091

CPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/0244

摘要： A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.

摘要翻译： 一种在P型半导体衬底中形成N型半导体层的半导体IC器件; N型层被P +型绝缘区划分成多个岛状区域; 并且在第一岛状区域中形成IIL，而在第二岛状区域中形成NPN晶体管，其中N型上扩散层从第一岛区的底部向上形成，而N型阱区为 从第一岛区域的表面向下形成，并且在第一岛区域和第二岛区域的底部附近形成N +型掩埋层。

公开(公告)号：US4998155A

公开(公告)日：1991-03-05

申请号：US73305

申请日：1987-07-13

申请人： Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/72 ,  H01L29/732

CPC分类号： H01L29/1008 ,  H01L29/1004 ,  H01L29/72 ,  Y10S257/906

摘要： A radiation-hardened semiconductor device including a bipolar transistor is disclosed in which a highly-doped layer equal in conductivity type to and larger in impurity concentration than the base region of the transistor is formed in that portion of the surface of the base region which exists beneath an insulating film, to prevent minority carriers injected into the base region, from reaching the above-mentioned surface portion. Thus, the injected minority carriers can reach a collector region without being extinguished by the recombination at the surface of the base region.

摘要翻译： 公开了一种包括双极晶体管的辐射硬化半导体器件，其中在存在的基极区域的表面部分中形成了与晶体管的基极区相比导电类型等于或大于杂质浓度的高掺杂层 在绝缘膜下面，以防止注入基底区域的少数载流子到达上述表面部分。 因此，注入的少数载流子可以到达集电极区，而不会被基区表面的复合所熄灭。

公开(公告)号：US4258330A

公开(公告)日：1981-03-24

申请号：US12028

申请日：1979-02-14

申请人： Kenji Kaneko ,  Takahiro Okabe ,  Tohru Nakamura ,  Wasao Takasugi ,  Minoru Nagata

发明人： Kenji Kaneko ,  Takahiro Okabe ,  Tohru Nakamura ,  Wasao Takasugi ,  Minoru Nagata

IPC分类号： H03F3/45 ,  H03K5/24 ,  H03K19/018 ,  H03K19/091

CPC分类号： H03K19/091 ,  H03F3/4508 ,  H03K19/01818 ,  H03K5/2409 ,  H03F2203/45344 ,  H03F2203/45394 ,  H03F2203/45674

摘要： A differential amplifier circuit wherein one collector of the multicollector of each of first, second and third inverse NPN transistors is connected to a base of the corresponding transistor; the first and second transistors are used as differential input transistors; the other collector of each of the first and second transistors is connected to a PNP transistor serving as a load current source; and an output is derived through the third transistor connected to the second transistor.

摘要翻译： 一种差分放大器电路，其中第一，第二和第三反向NPN晶体管中的每一个的多极集电极的一个集电极连接到相应晶体管的基极; 第一和第二晶体管用作差分输入晶体管; 第一和第二晶体管中的每一个的另一个集电极连接到用作负载电流源的PNP晶体管; 并且通过连接到第二晶体管的第三晶体管导出输出。

公开(公告)号：US4860086A

公开(公告)日：1989-08-22

申请号：US26254

申请日：1987-03-16

申请人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

发明人： Tohru Nakamura ,  Masahiko Ogirima ,  Kazuo Nakazato ,  Takao Miyazaki ,  Naoki Yamamoto ,  Minoru Nagata ,  Shojiro Sugaki, deceased

IPC分类号： H01L23/485 ,  H01L23/532

CPC分类号： H01L23/53271 ,  H01L23/485 ,  H01L2924/0002

摘要： A semiconductor device is constructed so that an insulation film is provided in regions other than a protruding portion of a substrate. A polycrystalline silicon layer and a metal silicide layer are formed over said insulation film to provide a multi-layer structure, and a take-out portion for at least one of the emitter, base, and collector members of a bipolar transistor provided in the mesa region is constituted by a film of this multi-layer structure. By virtue of the use of metal silicide together with the polycrystalline silicon, a very low resistance is achieved which enhances the device's operating speed. Further, the metal silicide is separated from the protruding portion of the substrate by a portion of the polycrystalline silicon to provide a smooth interface with the substrate. This smooth interface significantly reduces crystal defects in the single crystal substrate.

摘要翻译： 构造半导体器件，使得绝缘膜设置在除了衬底的突出部分之外的区域中。 在所述绝缘膜上形成多晶硅层和金属硅化物层以提供多层结构，以及设置在台面中的双极晶体管的发射极，基极和集电极构件中的至少一个的取出部分 区域由该多层结构的膜构成。 由于金属硅化物与多晶硅一起使用，所以实现了非常低的电阻，这增强了器件的工作速度。 此外，金属硅化物通过多晶硅的一部分与衬底的突出部分分离，以提供与衬底的平滑界面。 这种平滑的界面显着地减少了单晶衬底中的晶体缺陷。

公开(公告)号：US4429326A

公开(公告)日：1984-01-31

申请号：US96388

申请日：1979-11-21

申请人： Tomoyuki Watanabe ,  Kenji Kaneko ,  Tohru Nakamura ,  Yutaka Okada ,  Takahiro Okabe ,  Minoru Nagata ,  Yokichi Itoh ,  Toru Toyabe

发明人： Tomoyuki Watanabe ,  Kenji Kaneko ,  Tohru Nakamura ,  Yutaka Okada ,  Takahiro Okabe ,  Minoru Nagata ,  Yokichi Itoh ,  Toru Toyabe

IPC分类号： G11C11/411 ,  G11C14/00 ,  G11C16/04 ,  H01L27/02 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/091

CPC分类号： H01L27/0711 ,  G11C11/4113 ,  G11C14/00 ,  G11C16/0433 ,  G11C16/0466 ,  H01L27/0233 ,  H01L27/1022

摘要： An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

摘要翻译： 本发明的I2L型非易失性存储器具有这样的结构，其中浮置栅极通过I2L中的NPN晶体管的基极区附近的半导体层的表面上的绝缘膜设置。 本发明的I2L型非易失性存储器通过要存储在浮动栅极中的电荷来控制电流流过I2L的NPN晶体管的基极区域。 也就是说，I2L的NPN晶体管的集电极输出电流根据浮置栅极下面的通道的存在或不存在而被调制，这取决于浮置栅极内的电荷的存在或不存在以及浮置栅极的极性 收费。 结果，基极电流的变化在I2L的NPN晶体管的集电极端子处显示为输出信号，并且可以读出存储在浮动栅极中的数据。

公开(公告)号：US4819055A

公开(公告)日：1989-04-04

申请号：US189382

申请日：1988-05-02

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Takao Miyazaki ,  Nobuyoshi Natsuaki ,  Masahiko Ogirima ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Takao Miyazaki ,  Nobuyoshi Natsuaki ,  Masahiko Ogirima ,  Minoru Nagata

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/72 ,  H01L29/732 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L29/66272 ,  H01L21/8222 ,  H01L29/72 ,  H01L29/7325

摘要： The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer formed in the periphery of said semiconductor region thereby to reduce the parasitic capacitance, and wherein said insulation film is stretched and arranged on the lower side of said semiconductor region.

摘要翻译： 本发明涉及一种半导体器件，其包括第一导电类型的半导体衬底，形成在所述衬底上的半导体区域和设置在所述半导体区域和所述半导体衬底之间的第一绝缘膜，其中所述半导体衬底被所述绝缘体隔离 从形成在所述半导体区域的周围的多晶硅层形成的膜，从而减小寄生电容，并且其中所述绝缘膜被拉伸并布置在所述半导体区域的下侧。