公开(公告)号：US06462411B1

公开(公告)日：2002-10-08

申请号：US09205299

申请日：1998-12-04

申请人： Tomoji Watanabe ,  Nobuyuki Mise ,  Toshiyuki Uchino ,  Norio Suzuki ,  Yoshihiko Sakurai ,  Toshiya Uenishi ,  Yohsuke Inoue ,  Yasuhiro Inokuchi ,  Fumihide Ikeda

发明人： Tomoji Watanabe ,  Nobuyuki Mise ,  Toshiyuki Uchino ,  Norio Suzuki ,  Yoshihiko Sakurai ,  Toshiya Uenishi ,  Yohsuke Inoue ,  Yasuhiro Inokuchi ,  Fumihide Ikeda

IPC分类号： H01L2334

CPC分类号： H01L21/67748 ,  H01L21/67109 ,  H01L21/68735 ,  H01L21/6875 ,  H01L21/68785 ,  Y10T29/41

摘要： A semiconductor wafer processing apparatus comprises a reaction furnace capable of heating inside thereof, a wafer mount for mounting a semiconductor wafer thereon and a transfer device. The wafermount includes an opening which is greater than the semiconductor wafer and which has a circle shape or a shape substantially similar to an outer periphery of the semiconductor wafer, and includes a wafer supporting portion projecting inwardly of the opening for supporting the semiconductor wafer. The transfer device is capable of holding the wafer mount outside the semiconductor wafer as viewed from a vertical direction, and transferring the wafer mount carrying the semiconductor wafer thereon substantially horizontally into and/or out from the reaction furnace.

摘要翻译： 半导体晶片处理装置包括能够在其内部加热的反应炉，用于将半导体晶片安装在其上的晶片载体和转印装置。 所述瓦台车包括比所述半导体晶片大的开口部，该开口部具有与所述半导体晶片的外周大致相同的圆形或形状，并且具有向所述开口的内侧突出以支撑所述半导体晶片的晶片支撑部。 传送装置能够从垂直方向观察时将晶片安装体保持在半导体晶片外部，并将承载半导体晶片的晶片载体基本水平地转移到反应炉内和/或从反应炉出来。

公开(公告)号：US08404603B2

公开(公告)日：2013-03-26

申请号：US12825012

申请日：2010-06-28

申请人： Arito Ogawa ,  Sadayoshi Horii ,  Taketoshi Sato ,  Hideharu Itatani ,  Nobuyuki Mise ,  Osamu Tonomura

发明人： Arito Ogawa ,  Sadayoshi Horii ,  Taketoshi Sato ,  Hideharu Itatani ,  Nobuyuki Mise ,  Osamu Tonomura

IPC分类号： H01L21/31

CPC分类号： H01L21/31616 ,  C23C16/303 ,  C23C16/403 ,  C23C16/45525 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/68785 ,  H01L28/40

摘要： A method of manufacturing a semiconductor device. In the method, an aluminum-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminum precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminum precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminum-containing insulation film is formed on the aluminum-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber. In addition, heat treatment is performed on the substrate.

摘要翻译： 一种制造半导体器件的方法。 在该方法中，通过交替地重复将铝前体供给到容纳基板的处理室中并从处理室排出铝前体的工序，在基板的电极膜上形成含铝绝缘膜， 将氧化或氮化前体供应到处理室中并从处理室排出氧化或氮化前体的过程; 并且在含铝绝缘膜上形成与含铝绝缘膜不同的高介电常数绝缘膜，通过交替重复将前体供给到处理室中并从处理室排出前体的过程， 氧化前体进入处理室并从处理室排出氧化前体。 另外，对基板进行热处理。

公开(公告)号：US07671426B2

公开(公告)日：2010-03-02

申请号：US12320988

申请日：2009-02-10

申请人： Nobuyuki Mise ,  Akira Toriumi

发明人： Nobuyuki Mise ,  Akira Toriumi

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/7833

摘要： In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

摘要翻译： 在栅极长度为10nm以下的MIS晶体管中，包含形成在硅衬底上的氧化硅膜和在氧化硅膜上形成的高k膜的栅极绝缘体具有在侧面包含更多的氮的氮化区域 比在栅极长度方向的中央侧，并且在膜厚方向上在上侧包括比在下侧更多的氮。 使用包括高k（高介电常数）膜的栅极绝缘体的MIS晶体管的可靠性和特性得到增强。

公开(公告)号：US20080083956A1

公开(公告)日：2008-04-10

申请号：US11702104

申请日：2007-02-05

申请人： Nobuyuki Mise ,  Akira Toriumi

发明人： Nobuyuki Mise ,  Akira Toriumi

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/7833

摘要： In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

摘要翻译： 在栅极长度为10nm以下的MIS晶体管中，包含形成在硅衬底上的氧化硅膜和在氧化硅膜上形成的高k膜的栅极绝缘体具有在侧面包含更多的氮的氮化区域 比在栅极长度方向的中央侧，并且在膜厚方向上在上侧包括比在下侧更多的氮。 使用包括高k（高介电常数）膜的栅极绝缘体的MIS晶体管的可靠性和特性得到增强。

公开(公告)号：US06759253B2

公开(公告)日：2004-07-06

申请号：US09788629

申请日：2001-02-16

申请人： Tatehito Usui ,  Tetsuo Ono ,  Ryoji Nishio ,  Kazue Takahashi ,  Nobuyuki Mise

发明人： Tatehito Usui ,  Tetsuo Ono ,  Ryoji Nishio ,  Kazue Takahashi ,  Nobuyuki Mise

IPC分类号： H01L21302

CPC分类号： H01L22/34 ,  C23C16/50 ,  C23C16/52 ,  G01N21/73 ,  H01J37/32935 ,  H01L21/67253 ,  H01L2924/0002 ,  H01L2924/00

摘要： The intensity of the light emitted from the light-emitting diode on wafer is measured and then the potential difference between the terminals of the light-emitting element, and the plasma current flowing thereinto are derived from measured light intensity. Since the use of a camera enables non-contact measurement of emitted light intensity, the lead-in terminals for lead wires that are always required in conventional probing methods become unnecessary. In addition, since the target wafer does not require lead wire connection, wafers can be changed in the same way as performed for etching.

摘要翻译： 测量从晶片上的发光二极管发射的光的强度，然后从测量的光强度导出发光元件的端子与其中流动的等离子体电流之间的电位差。 由于使用相机能够非接触地测量发射的光强度，所以在常规探测方法中始终需要的导线的引入端子变得不必要。 此外，由于目标晶片不需要引线连接，因此可以以与蚀刻相同的方式来改变晶片。

公开(公告)号：US5242539A

公开(公告)日：1993-09-07

申请号：US859336

申请日：1992-03-27

申请人： Takao Kumihashi ,  Kazunori Tsujimoto ,  Shinichi Tachi ,  Masafumi Kanetomo ,  Junichi Kobayashi ,  Tatehito Usui ,  Nobuyuki Mise

发明人： Takao Kumihashi ,  Kazunori Tsujimoto ,  Shinichi Tachi ,  Masafumi Kanetomo ,  Junichi Kobayashi ,  Tatehito Usui ,  Nobuyuki Mise

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/02071 ,  H01J37/32082 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32834 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32137 ,  H01J2237/3322 ,  H01J2237/3343

摘要： A plasma treatment method and apparatus utilize various gas inlet and outlet structure arrangements to optimize treatment characteristics for a semiconductor wafer. A buffer zone is created between gas inlets and the discharge zone of the vacuum treatment chamber to enhance uniformity of gas flow. The evacuation arrangement enables reactant gas to be exhausted uniformly to reduce gas residence time below a threshold while maintaining optimum flow rates and etch uniformity at low effective exhaust speeds.

摘要翻译： 等离子体处理方法和装置利用各种气体入口和出口结构布置来优化半导体晶片的处理特性。 在气体入口和真空处理室的排放区之间产生缓冲区，以增强气体流动的均匀性。 排气装置使反应气体均匀排气，以将气体停留时间降低到阈值以下，同时在低有效排气速度下保持最佳流速和蚀刻均匀性。

公开(公告)号：US08288221B2

公开(公告)日：2012-10-16

申请号：US12537875

申请日：2009-08-07

申请人： Takahisa Eimori ,  Nobuyuki Mise

发明人： Takahisa Eimori ,  Nobuyuki Mise

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02321 ,  H01L21/31612 ,  H01L21/31645 ,  H01L21/823842 ,  H01L27/11 ,  H01L27/1104

摘要： A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.

摘要翻译： 在形成在基板的主表面上的氧化硅（SiO 2）膜上形成含有铪和氧的基极绝缘膜。 随后，在基底绝缘膜上形成比基底绝缘膜薄且仅由金属元件制成的金属薄膜，并且在金属薄膜上形成具有耐湿性和抗氧化性的保护膜。 然后，通过在具有保护膜的状态下将金属薄膜的整个金属元素扩散到基底绝缘膜中，比硅氧化膜厚且具有比硅更高的介电常数的混合膜（高介电常数膜） 在氧化硅膜上形成氧化物并含有基底绝缘膜的铪和氧和金属薄膜的金属元素。

公开(公告)号：US07968396B2

公开(公告)日：2011-06-28

申请号：US12591648

申请日：2009-11-25

申请人： Yukimune Watanabe ,  Shinji Migita ,  Nobuyuki Mise

发明人： Yukimune Watanabe ,  Shinji Migita ,  Nobuyuki Mise

IPC分类号： H01L21/336

CPC分类号： H01L29/41766 ,  H01L21/2257 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78609

摘要： A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.

摘要翻译： 半导体器件包括形成在绝缘层上的半导体层; 栅极，经由栅极绝缘膜设置在所述半导体层上; 源极/漏极层，其通过包括合金层或具有与所述绝缘层接触的底面的金属层构成，所述源极/漏极层具有沿着所述半导体层的晶体取向面设置的沟道区的接合表面; 以及沿着合金层或金属层的界面以自对准的方式形成的杂质掺杂层和所述半导体层。

公开(公告)号：US20100072551A1

公开(公告)日：2010-03-25

申请号：US12591648

申请日：2009-11-25

申请人： Yukimune Watanabe ,  Shinji Migita ,  Nobuyuki Mise

发明人： Yukimune Watanabe ,  Shinji Migita ,  Nobuyuki Mise

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/41766 ,  H01L21/2257 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78609

摘要： A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.

摘要翻译： 半导体器件包括形成在绝缘层上的半导体层; 栅极，经由栅极绝缘膜设置在所述半导体层上; 源极/漏极层，其通过包括合金层或具有与所述绝缘层接触的底面的金属层构成，所述源极/漏极层具有沿着所述半导体层的晶体取向面设置的沟道区的接合表面; 以及沿着合金层或金属层的界面以自对准的方式形成的杂质掺杂层和所述半导体层。

公开(公告)号：US07507632B2

公开(公告)日：2009-03-24

申请号：US11702104

申请日：2007-02-05

申请人： Nobuyuki Mise ,  Akira Toriumi

发明人： Nobuyuki Mise ,  Akira Toriumi

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/7833

摘要： In a MIS transistor of which gate length is 10 nm or less, a gate insulator comprising a silicon oxide film formed on a silicon substrate and a high-k film formed on the silicon oxide film has a nitrided region including more nitrogen at the lateral side than at the central side in the gate-length direction, and including more nitrogen at the upper side than at the lower side in the film thickness direction. The reliability and characteristics of a MIS transistor using a gate insulator including a high-k (high dielectric constant) film is enhanced.

摘要翻译： 在栅极长度为10nm以下的MIS晶体管中，包含形成在硅衬底上的氧化硅膜和在氧化硅膜上形成的高k膜的栅极绝缘体具有在侧面包含更多的氮的氮化区域 比在栅极长度方向的中央侧，并且在膜厚方向上在上侧包括比在下侧更多的氮。 使用包括高k（高介电常数）膜的栅极绝缘体的MIS晶体管的可靠性和特性得到增强。