公开(公告)号：US20050224939A1

公开(公告)日：2005-10-13

申请号：US11100541

申请日：2005-04-07

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/603 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/2989 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/8182 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: As illustrated in FIG. 2(a), a wiring pattern 2 is provided on an insulating tape 1. Part of the wiring pattern 2 is a connection section 4 for connection. As illustrated in FIG. 2(b), an insulating resin 7 is provided so that the connection section 4 is coated with the insulating resin 7. As illustrated in FIG. 2(c), a protrusion electrode 6 of a semiconductor element 3 is so positioned on the connection section 4 so that the protrusion electrode 6 will push away the insulating resin 7 and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. As illustrated in FIG. 2(d), heat is applied while pressing in Direction D1. In this way, the connection section 4 intrudes into the protrusion electrode 6, thereby causing the connection section 4 and the protrusion electrode 6 to be connected with each other. With this, it is possible to provide a COF semiconductor device having better bonding strength between the tape and the semiconductor element.

Abstract translation: 如图1所示。 如图2（a）所示，布线图案2设置在绝缘带1上。布线图案2的一部分是连接用连接部4。 如图1所示。 如图2（b）所示，设置绝缘树脂7，使得连接部4涂覆有绝缘树脂7。 如图2（c）所示，半导体元件3的突起电极6位于连接部4上，突出电极6将推开绝缘树脂7并与连接部连接。 然后，按照方向D 1按压半导体。 如图2（d）所示，在方向D 1中按压时施加热量。这样，连接部4入侵突起电极6，从而使连接部4和突起电极6相互连接。 由此，可以提供在带和半导体元件之间具有更好的接合强度的COF半导体器件。

公开(公告)号：US06710458B2

公开(公告)日：2004-03-23

申请号：US09975066

申请日：2001-10-12

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L2348

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A dummy pattern for preventing generation of air bubbles in resin sealing of a semiconductor element is provided at a corner of the semiconductor element on a tape carrier which is composed of a polyimide-based insulating tape and a copper foil pattern formed thereon. The dummy pattern makes it possible to control flow of sealing resin from the corner of the semiconductor element to a space between a lower surface of the semiconductor element and the insulating tape, resulting in prevention of air bubbles generated in resin sealing of the semiconductor element. A generation rate of air bubble can be decreased to 50% or less as compared with a conventional COF semiconductor device.

Abstract translation: 在由聚酰亚胺系绝缘带和形成在其上的铜箔图案构成的带载体上的半导体元件的角部设置用于防止半导体元件的树脂密封中产生气泡的虚拟图案。 虚设图案使得可以控制密封树脂从半导体元件的角度到半导体元件的下表面与绝缘带之间的空间的流动，从而防止半导体元件的树脂密封中产生的气泡。 与常规COF半导体器件相比，气泡的产生速率可以降低到50％以下。

公开(公告)号：US06388888B1

公开(公告)日：2002-05-14

申请号：US09597582

申请日：2000-06-20

Applicant: Toshiharu Seko ,  Kenji Toyosawa

Inventor： Toshiharu Seko ,  Kenji Toyosawa

IPC: H05K710

CPC classification number: H05K3/0097 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K3/007 ,  H05K2201/2009 ,  H05K2203/0156 ,  H05K2203/1545 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.

Abstract translation: 一种半导体器件，包括图案化布线，其包括形成在细长基底膜上的用于外部连接的连接器，半导体元件或半导体元件以及安装在与用于连接图案化布线的部分电连接的半导体元件之外的部件， 一个细长的加强构件，设置在与形成图案的布线的表面相对的基底膜的表面上，该加强构件在与基膜的纵向侧面相对应的位置处具有链轮孔，其中该加强构件还设置在 所述相对的底膜表面在与其上形成有用于外部连接的连接器的区域相对应的区域中。

公开(公告)号：US20130058074A1

公开(公告)日：2013-03-07

申请号：US13559645

申请日：2012-07-27

Applicant: Junichi SOMEI ,  Toshiharu Seko

Inventor： Junichi SOMEI ,  Toshiharu Seko

IPC: F21S8/00

CPC classification number: F21V13/04 ,  F21S4/28 ,  F21V9/30 ,  F21V11/14 ,  F21V23/0464 ,  F21V23/0471 ,  F21V33/006 ,  F21W2111/08 ,  F21Y2107/90 ,  F21Y2115/10

Abstract: A handrail with an illumination function includes: a handrail main body; a decorative cover that is disposed at part of the handrail main body so as to extend along a longitudinal direction of the handrail main body and has a light transmitting property; a flatter that is disposed on an inner side with respect to the decorative cover so as to extend along the longitudinal direction of the handrail main body and reflects and diffuses light to radiate the light through a slit; and a light source that is disposed on an inner side of the flatter.

Abstract translation: 具有照明功能的扶手包括：扶手主体; 装饰盖，其设置在扶手主体的一部分上，以沿着扶手主体的长度方向延伸并具有透光性; 相对于装饰盖的内侧设置成沿着扶手主体的长度方向延伸，并且反射并漫射光以通过狭缝辐射光; 以及设置在更平坦的内侧的光源。

公开(公告)号：US20080251946A1

公开(公告)日：2008-10-16

申请号：US12068498

申请日：2008-02-07

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L23/498

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/4985 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0269 ,  H05K1/189 ,  H05K3/281 ,  H05K3/284 ,  H05K3/303 ,  H05K3/305 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract translation: 本发明的半导体装置包括：（i）具有绝缘基板的线基板，其中设置有多个线图案，（ii）半导体元件，其安装在线基板上，绝缘树脂插入其间，多个 设置在半导体元件中的连接端子分别电连接到导线图案的连接端子。 在半导体装置中，绝缘基板具有用于对准半导体元件的连接端子和导线图案的连接端子的标记图案，并且每个标记图案的整个上表面被绝缘树脂覆盖。

公开(公告)号：US07053494B2

公开(公告)日：2006-05-30

申请号：US10839334

申请日：2004-05-06

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L21/48 ,  H01L29/40

CPC classification number: H01L24/32 ,  H01L23/49811 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.

Abstract translation: 半导体器件包括其表面上设置有互连图案的薄膜基板，安装在薄膜基板上并具有设置在其表面上的电极的半导体芯片，以及设置在薄膜基板和半导体芯片之间的绝缘树脂部分， 所述树脂部分是通过在所述薄膜基片和所述半导体芯片中的至少一个上施加绝缘树脂而形成的，并且当所述半导体芯片安装在所述薄膜基片上时，用所述树脂填充所述薄膜基片和所述半导体芯片之间的空间， 其中所述互连图案具有突起，所述突起具有朝向所述半导体芯片的电极渐缩的截面形状并且侵入所述电极，从而与所述电极电连接。

公开(公告)号：US20050218513A1

公开(公告)日：2005-10-06

申请号：US11091918

申请日：2005-03-29

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L21/60 ,  H01L21/44 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/12 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H05K3/28 ,  H05K3/30

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/4985 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0269 ,  H05K1/189 ,  H05K3/281 ,  H05K3/284 ,  H05K3/303 ,  H05K3/305 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract translation: 本发明的半导体装置包括：（i）具有绝缘基板的线基板，其中设置有多个线图案，（ii）半导体元件，其安装在线基板上，绝缘树脂插入其间，多个 设置在半导体元件中的连接端子分别电连接到导线图案的连接端子。 在半导体装置中，绝缘基板具有用于对准半导体元件的连接端子和导线图案的连接端子的标记图案，并且每个标记图案的整个上表面被绝缘树脂覆盖。

公开(公告)号：US07750457B2

公开(公告)日：2010-07-06

申请号：US12068498

申请日：2008-02-07

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/4985 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0269 ,  H05K1/189 ,  H05K3/281 ,  H05K3/284 ,  H05K3/303 ,  H05K3/305 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract translation: 本发明的半导体装置包括：（i）具有绝缘基板的线基板，其中设置有多个线图案，（ii）半导体元件，其安装在线基板上，绝缘树脂插入其间，多个 设置在半导体元件中的连接端子分别电连接到导线图案的连接端子。 在半导体装置中，绝缘基板具有用于对准半导体元件的连接端子和导线图案的连接端子的标记图案，并且每个标记图案的整个上表面被绝缘树脂覆盖。

公开(公告)号：US07671454B2

公开(公告)日：2010-03-02

申请号：US11798232

申请日：2007-05-11

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.

Abstract translation: 本发明的带载体包括绝缘带和形成在绝缘带上的布线图案。 布线图案包括连接部分，布线图案经由该连接部分连接到凸块电极。 连接部设置在布线图案的重叠部分的一部分处，当半导体器件安装在布线图案上时，该重叠部分与半导体器件重叠。 布线图案的连接部分的布线宽度比重叠部分的剩余部分小，该剩余部分不是连接部分。

公开(公告)号：US07582976B2

公开(公告)日：2009-09-01

申请号：US11896827

申请日：2007-09-06

Applicant: Toshiharu Seko ,  Kenji Toyosawa

Inventor： Toshiharu Seko ,  Kenji Toyosawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/4985 ,  H01L21/4821 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49572 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/0097 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0

Abstract translation: 本发明提供一种由薄膜绝缘带1形成的半导体器件带载体，其通过在其表面上将多个线图案11导引到半导体元件21的凸块23而成为半导体器件，并被密封 绝缘树脂22，其中：半导体器件在绝缘带1的滑动方向上的外部尺寸大于间距间隔的整数倍X（X = 1,2,3,4,5等） 的链轮孔2，其为形成为承载绝缘带1的开口，并且不大于：整数倍X +十进制Y（0