利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.027 秒)

    Polishing apparatus
    1.
    发明授权
    Polishing apparatus 失效
    抛光设备

    公开(公告)号：US5655954A

    公开(公告)日：1997-08-12

    申请号：US564520

    申请日：1995-11-29

    申请人： Toshio Oishi ,  Shoichi Shin ,  Masafumi Tsunada ,  Masahiro Ishida ,  Yasukazu Mase

    发明人： Toshio Oishi ,  Shoichi Shin ,  Masafumi Tsunada ,  Masahiro Ishida ,  Yasukazu Mase

    IPC分类号： B08B1/04 ,  B24B37/10 ,  B24B37/34 ,  B24B53/007 ,  B24B53/017 ,  B24B55/06 ,  H01L21/00 ,  B24B7/00 ,  B24B9/00

    CPC分类号： B24B37/107 ,  B08B1/04 ,  B24B37/345 ,  B24B53/017 ,  B24B55/06 ,  H01L21/67028

    摘要： Provided is a polishing apparatus which comprises a polishing mechanism for polishing a wafer taken out from a cassette, an attaching-detaching device for attaching to and detaching the wafer from the polishing mechanism, a device for cleaning the polished wafer, and a transportation device for transporting the wafer between the cassette, polishing mechanism, attaching-detaching device, and cleaning device. These devices are arranged individually in compartments. A working chamber is divided into a plurality of compartments by means of partitioning devices. A device for polishing a workpiece is set in one of the compartments. The apparatus is also provided with communication devices for internally connecting the adjacent compartments which are divided by the partitioning devices. The apparatus may further comprise devices for individually controlling the respective internal pressures of the compartments or a device for generating an air flow in the form of a laminar flow in each of the compartments.

    摘要翻译： 本发明提供一种研磨装置，其特征在于，包括：研磨从盒取出的晶片的研磨机构，将所述晶片与所述研磨机构连接并从所述研磨机构拆下的安装拆卸装置， 在盒，抛光机构，安装拆卸装置和清洁装置之间传送晶片。 这些设备分别安装在隔间中。 工作室通过分隔装置分成多个隔间。 用于抛光工件的装置设置在隔室中的一个中。 该装置还设置有用于内部连接由分隔装置划分的相邻隔室的通信装置。 该装置还可以包括用于单独控制隔室的相应内部压力的装置或用于在每个隔间中产生层流形式的空气流的装置。

    Method of controlling metal thin film formation conditions
    5.
    发明授权
    Method of controlling metal thin film formation conditions 失效
    控制金属薄膜形成条件的方法

    公开(公告)号：US5175115A

    公开(公告)日：1992-12-29

    申请号：US654488

    申请日：1991-02-13

    申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

    发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

    IPC分类号： H01L21/48

    CPC分类号： H01L21/4846

    摘要： Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

    摘要翻译： 进行在Si衬底上形成的Al薄膜的温度 - 内部应力特性的测量。 可以根据测量的特性获得混合在薄膜中的杂质或杂质的量。 当温度升高时获得的特性中，薄膜中Al原子的迁移开始温度作为信息反馈到薄膜形成步骤，从而控制用于形成薄膜的气氛中的杂质量。

    Method for planarizing the surface of an interlayer insulating film in a semiconductor device
    6.
    发明授权
    Method for planarizing the surface of an interlayer insulating film in a semiconductor device 失效
    在半导体器件中对层间绝缘膜的表面进行平面化的方法

    公开(公告)号：US4634496A

    公开(公告)日：1987-01-06

    申请号：US797986

    申请日：1985-11-14

    申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

    发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

    IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76819

    摘要： A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.

    摘要翻译： 一种用于平坦化沉积在第一互连层上的绝缘层的表面以允许沉积在其上的第二互连层而不引起第二互连层的破损的方法。 该方法的特征在于，首先在第一互连层上形成至少两个彼此不同的蚀刻特性的绝缘膜，然后在第二绝缘膜上沉积抗蚀剂层。 随后，蚀刻抗蚀剂层的一部分以暴露第二绝缘膜的顶表面，并且使用剩余的抗蚀剂层作为掩模来选择性地和各向异性地蚀刻第二绝缘膜。 在去除第一绝缘膜和剩余的抗蚀剂标记之后，沉积第三绝缘膜至足以使其表面平坦的厚度。

    Method of forming multilayered wiring structure of semiconductor device
    7.
    发明授权
    Method of forming multilayered wiring structure of semiconductor device 失效
    形成半导体器件多层布线结构的方法

    公开(公告)号：US5258328A

    公开(公告)日：1993-11-02

    申请号：US31324

    申请日：1993-03-15

    申请人： Takeshi Sunada ,  Yasukazu Mase

    发明人： Takeshi Sunada ,  Yasukazu Mase

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/461

    CPC分类号： H01L23/5226 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S438/927

    摘要： A conductive film is formed on first and second prospective lower wiring layer formation regions on a semiconductor substrate and a prospective isolation region between the lower wiring layers. An insulating interlayer is formed on the semiconductor substrate including this conductive film and is partially removed to obtain an opening in which the conductive film is exposed. In addition, an upper wiring layer is formed on the upper surface of the semiconductor substrate. The conductive film and an upper wiring portion located on the conductive film are simultaneously and selectively removed to obtain isolated upper layer portions and isolated conductive film portions. Alternatively, two wiring portions each having at least two lower wiring portions electrically insulated from each other and adjacent to each other are formed on a semiconductor substrate having a stepped portion, and an insulating interlayer is formed thereon. The insulating interlayer is removed until the first and second wiring portions are exposed. In addition, the stepped portion formed in the second wiring portion is buried with a third insulating film. A method of forming a highly reliable multilayered wiring structure at a high yield can be obtained.

    摘要翻译： 导电膜形成在半导体衬底上的第一和第二预期下布线层形成区域和下布线层之间的前视隔离区域。 在包括该导电膜的半导体基板上形成绝缘中间层，并且被部分地去除以获得其中暴露导电膜的开口。 此外，在半导体衬底的上表面上形成上部布线层。 同时选择性地去除位于导电膜上的导电膜和上布线部分，以获得隔离的上层部分和隔离的导电膜部分。 或者，在具有阶梯部的半导体基板上形成有具有彼此电绝缘并彼此相邻的至少两个下部布线部的两个布线部，并且在其上形成绝缘中间层。 去除绝缘中间层直到第一和第二布线部分露出。 此外，形成在第二布线部分中的台阶部分被第三绝缘膜掩埋。 可以获得以高产率形成高可靠性多层布线结构的方法。