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    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed
    5.
    再颁专利
    Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
    大容量半导体存储器，具有改进的子放大器布局，以提高速度

    公开(公告)号：USRE42659E1

    公开(公告)日：2011-08-30

    申请号：US11759316

    申请日：2007-06-07

    申请人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    发明人： Tsugio Takahashi ,  Goro Kitsukawa ,  Takesada Akiba ,  Yasushi Kawase ,  Masayuki Nakamura

    IPC分类号： G11C8/00

    CPC分类号： H01L27/10805 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/105

    摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

    摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。

    ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit
    6.
    发明授权
    ZQ calibration circuit and a semiconductor device including a ZQ calibration circuit 有权
    ZQ校准电路和包括ZQ校准电路的半导体器件

    公开(公告)号：US07839159B2

    公开(公告)日：2010-11-23

    申请号：US11585108

    申请日：2006-10-24

    申请人： Masayuki Nakamura ,  Hideyuki Yoko

    发明人： Masayuki Nakamura ,  Hideyuki Yoko

    IPC分类号： G01R31/26

    CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

    摘要： A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

    摘要翻译： ZQ校准命令在内部从与ZQ校准命令不同的外部命令生成，以便自动执行附加的ZQ校准操作。 有效地采用输入命令和下一命令之间的命令间隔来获得ZQ校准周期。 与ZQ校准命令不同的外部命令优选为自刷新命令。 添加ZQ校准操作可缩短ZQ校准操作之间的间隔。 因此，可以更精确地获得能够执行ZQ校准操作的ZQ校准电路。

    MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM
    7.
    发明申请
    MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM 有权
    存储器访问控制电路和图像处理系统

    公开(公告)号：US20100123728A1

    公开(公告)日：2010-05-20

    申请号：US12608322

    申请日：2009-10-29

    申请人： Akihiro KAWAHARA ,  Makoto Adachi ,  Kouji Nishikawa ,  Masayuki Nakamura ,  Motonobu Mamiya ,  Kae Yamashita

    发明人： Akihiro KAWAHARA ,  Makoto Adachi ,  Kouji Nishikawa ,  Masayuki Nakamura ,  Motonobu Mamiya ,  Kae Yamashita

    IPC分类号： G06F13/00 ,  G06F12/16

    CPC分类号： G09G5/397 ,  G09G5/363 ,  G09G5/393

    摘要： A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

    摘要翻译： 存储器访问控制电路包括第一内部寄存器，地址发送单元，其将第一内部寄存器的状态设置为第一状态以发送第一地址，并将第一内部寄存器的状态设置为第二状态，以发送第二内部寄存器 地址，第二内部寄存器，数据接收单元，其将第二内部寄存器的状态设置为第三状态，以接收对应于第一地址的第一数据，对延迟的第一数据执行数据处理，设置第二内部寄存器的状态 内部寄存器到第四状态以接收对应于第二地址的第二数据，并且在延迟给定延迟时间的第二数据之后对第二数据执行数据处理，第一备份单元和第二备份单元。

    SPIROCHROMANON DERIVATIVES
    8.
    发明申请
    SPIROCHROMANON DERIVATIVES 有权
    螺吡喃衍生物

    公开(公告)号：US20090270436A1

    公开(公告)日：2009-10-29

    申请号：US12518466

    申请日：2008-01-08

    申请人： Tomoharu Iino ,  Hideki Jona ,  Hideki Kurihara ,  Masayuki Nakamura ,  Kenji Niiyama ,  Jun Shibata ,  Tadashi Shimamura ,  Hitomi Watanabe ,  Takeru Yamakawa ,  Lihu Yang

    发明人： Tomoharu Iino ,  Hideki Jona ,  Hideki Kurihara ,  Masayuki Nakamura ,  Kenji Niiyama ,  Jun Shibata ,  Tadashi Shimamura ,  Hitomi Watanabe ,  Takeru Yamakawa ,  Lihu Yang

    IPC分类号： A61K31/438 ,  C07D401/14 ,  A61P3/00 ,  A61P35/00 ,  A61P31/00

    CPC分类号： C07D491/107 ,  C07D491/20 ,  C07D519/00

    摘要： The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-b]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3: R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a nitrogen atom or a machine group; and V represents an oxygen atom or a sulfur atom. The compound of the invention is useful as therapeutical agents for various ACC-related diseases.

    摘要翻译： 本发明涉及通式（I）的化合物：其中Ar 1表示由选自苯，吡唑，异恶唑，吡啶，吲哚，1H-吲唑，1H-呋喃并[ 3-c]吡唑，1H-噻吩并[2,3-c]吡唑，苯并咪唑，1,2-苯并异恶唑，咪唑并[1,2-a]吡啶，咪唑并[1,5-a]吡啶和1H-吡唑并[ 具有Ar 2且任选具有一个或两个以上选自R 3：R 1和R 2的取代基的3,4-b]吡啶各自独立地表示氢原子，卤素原子，氰基，C 2 -C 6烯基， C1-C6烷氧基，C2-C7烷酰基，C2-C7烷氧基羰基，芳烷氧基羰基，氨基甲酰基C1-C6烷氧基，羧基-C2-C6链烯基或-Q1-N （Ra）-Q2-Rb; 或任选具有取代基的C1-C6烷基; 或任选具有取代基的芳基或杂环基; 或具有芳基或杂环基的C 1 -C 6烷基或C 2 -C 6烯基; T和U各自独立地表示氮原子或机组; V表示氧原子或硫原子。 本发明的化合物可用作各种ACC相关疾病的治疗剂。

    Reference voltage generating circuit
    9.
    发明授权
    Reference voltage generating circuit 有权
    基准电压发生电路

    公开(公告)号：US07541862B2

    公开(公告)日：2009-06-02

    申请号：US11603121

    申请日：2006-11-22

    申请人： Hiroki Fujisawa ,  Masayuki Nakamura ,  Hitoshi Tanaka

    发明人： Hiroki Fujisawa ,  Masayuki Nakamura ,  Hitoshi Tanaka

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： G05F3/30

    摘要： A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.

    摘要翻译： 描述参考电压产生电路。 该电路包括产生具有正温度系数的第一电流的电流产生部分，产生具有负温度系数的电压的电压产生部分，产生与具有正温度的电压之和的电压的合成部分 系数，并且在电压具有负温度系数的电阻器的两端开发，以及产生具有正温度系数的第二电流的补偿电流产生部。 使与第一和第二电流之和相对应的电流流过电阻器。 合成部分产生电阻的端点电压与第一和第二电流的和电流与负温度系数的电压之和的电压。