公开(公告)号：US5994739A

公开(公告)日：1999-11-30

申请号：US478654

申请日：1995-06-07

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18 ,  H01L27/12 ,  H01L29/739 ,  H01L27/01

CPC分类号： H01L29/7394 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1203 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/73227 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： An integrated circuit device comprising an active layer of a first conductivity type insulatively disposed over a semiconductor substrate, a lateral bipolar transistor fabricated in the active layer, the lateral bipolar transistor comprising a first base layer of a second conductivity type which is formed in the active layer, an emitter layer of the first conductivity, and a collector of the first conductivity which is formed in the active layer on a lateral side of the first base layer, a MOS transistor fabricated in the active layer, the MOS transistor comprising a second base layer of the second conductivity type, a source layer of the first conductivity type which is formed in the second base layer, a drain layer of the first conductivity type which is formed in the active layer, and a gate electrode insulatively disposed over the second base layer between the source layer and the drain layer, and an isolation layer formed in the active layer for separating the bipolar transistor and the MOS transistor from each other.

摘要翻译： 一种集成电路装置，包括绝缘地设置在半导体衬底上的第一导电类型的有源层，在有源层中制造的横向双极晶体管，所述横向双极晶体管包括形成在有源层中的第二导电类型的第一基极层 层，第一导电性的发射极层和形成在第一基极层的侧面的有源层中的第一导电性的集电体，制造在有源层中的MOS晶体管，所述MOS晶体管包括第二基极 第二导电类型的层，形成在第二基极层中的第一导电类型的源极层，形成在有源层中的第一导电类型的漏极层和绝缘地设置在第二基极上的栅电极 源极层和漏极层之间的层，以及形成在用于分离双极晶体管a的有源层中的隔离层 并将MOS晶体管彼此连接起来。

公开(公告)号：US5714782A

公开(公告)日：1998-02-03

申请号：US745248

申请日：1996-11-08

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/8234 ,  H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/00 ,  H01L27/01 ,  H01L27/082 ,  H01L27/088 ,  H01L27/12 ,  H01L27/15 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L31/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7317 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/7436 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon.

摘要翻译： 复合集成电路器件包括半导体元件芯片，形成在半导体元件芯片上的定位引导件和通过定位引导件以自对准方式设置在半导体元件芯片上的预设位置的电子元件并安装在其上 。

公开(公告)号：US5144401A

公开(公告)日：1992-09-01

申请号：US386763

申请日：1989-07-31

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/744 ,  H01L29/749

CPC分类号： H01L29/749 ,  H01L29/744

摘要： A thyristor is disclosed which has a laminated structure of a first emitter layer of n.sup.+ conductivity type, a first base layer of p type, a second base layer of p.sup.- type, a second emitter layer of n type, and a second emitter layer of p.sup.+ type. The first base layer has a first exposed surface portion which is in lateral contact with the first emitter layer, and a second exposed surface portion which is in lateral contact with the second base layer. The second surface portion defines a layer portion of the second base layer which is positioned between the first base layer and the second emitter layer. An anode electrode is connected to said second emitter layer, whereas a cathode electrode is connected to the second base layer and the first emitter layer. A first gate electrode is formed on the first surface portion of the first base layer. A second gate electrode is insulatively disposed above the second surface portion of the first base layer to form a MOSFET together with the first base layer and the second emitter layer. The layer portion of the second base layer serves as a channel region of the MOSFET.

摘要翻译： 公开了一种晶闸管，其具有n +导电类型的第一发射极层，p型的第一基极层，p型的第二基极层，n型的第二发射极层和n型的第二发射极层 p +型。 第一基层具有与第一发射极层侧向接触的第一暴露表面部分和与第二基底层侧向接触的第二暴露表面部分。 第二表面部分限定位于第一基底层和第二发射体层之间的第二基底层的层部分。 阳极电极连接到所述第二发射极层，而阴极连接到第二基极层和第一发射极层。 第一栅电极形成在第一基层的第一表面部分上。 第二栅电极被绝对地设置在第一基极层的第二表面部分上方，以与第一基极层和第二发射极层一起形成MOSFET。 第二基极层的层部分用作MOSFET的沟道区。

公开(公告)号：US5049968A

公开(公告)日：1991-09-17

申请号：US486395

申请日：1990-02-28

申请人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

发明人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/763 ,  H01L27/088 ,  H01L27/12 ,  H01L29/739

CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286

摘要： A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

摘要翻译： 介电隔离的基板包括第一半导体晶片，接合在第一半导体晶片上的第二半导体晶片，其间插入有第一绝缘层，形成在第二半导体晶片上的半导体层，形成在半导体层中的第一沟槽和第二半导体 晶片，以便到达第一绝缘层，由此隔离半导体层和第二半导体晶片以及形成在第一凹槽的侧面上或嵌入第一凹槽中的第二绝缘层。 在该介电隔离基板中，在由第一凹槽隔离的区域中形成高击穿电压元件和低击穿电压元件。

公开(公告)号：US5315134A

公开(公告)日：1994-05-24

申请号：US896422

申请日：1992-06-10

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455

摘要： A thyristor with an insulated gate includes a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. A drain electrode contacting the p-type base layer is formed adjacent to one side of the n-type emitter layer. An n-type drain layer, which is short-circuited with the p-type base layer by the drain electrode, is formed. An n-type source layer is formed a predetermined distance away from the n-type drain layer. A turn-off insulated gate is formed between the n-type source layer and the n-type drain layer. A source electrode is connected to a cathode electrode. Thereby, turn-off capability of the thyristor can be improved.

摘要翻译： 具有绝缘栅的晶闸管包括p型发射极层，n型基极层，p型基极层和n型发射极层。 与p型基极层接触的漏电极与n型发射极层的一侧相邻地形成。 形成了由漏电极与p型基极层短路的n型漏极层。 n型源极层与n型漏极层形成规定的距离。 在n型源极层和n型漏极层之间形成有截止绝缘栅极。 源电极连接到阴极电极。 由此，能够提高晶闸管的关断能力。

公开(公告)号：US5159427A

公开(公告)日：1992-10-27

申请号：US588544

申请日：1990-09-26

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L21/761

摘要： A wafer substrate structure has a P type epitaxial wafer layer. An N+ type region separation layer is formed on the wafer layer to define a first closed region and a second region neighboring thereto. Formed in the first region are a P- type layer and an N- type layer stacked thereon and serving as a high-resistance layer for forming the first element. An N- type layer serving as a high-resistance layer exists in the second region of the wafer layer. These high-resistance layers are defined by separating a single semiconductor layer by an N+ type diffused separation layer. Forming a high-voltage transistor as a power element in the first region to be PN junction-separated brings a "double PN junction separation" structure wherein the first region is electrically separated by a PN junction from the second region and the high-voltage transistor is also PN junction-separated in the first region.

公开(公告)号：US5097314A

公开(公告)日：1992-03-17

申请号：US732575

申请日：1991-07-18

申请人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

发明人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/763 ,  H01L27/088 ,  H01L27/12 ,  H01L29/739 ,  H01L27/02 ,  H01L27/04

CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286

摘要： A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semicondcutor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

公开(公告)号：US4959703A

公开(公告)日：1990-09-25

申请号：US373279

申请日：1989-06-28

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

CPC分类号： H01L29/102 ,  H01L29/0834 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

摘要： A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and fuctioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application. At this time, charge carriers exhausted from the second emitter layer are allowed to flow into the first base layer through the channel region of the MOSFET, thereby suppressing the local concentration of the turn-off current in the thyristor.

公开(公告)号：US5477065A

公开(公告)日：1995-12-19

申请号：US191132

申请日：1994-01-24

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/8234 ,  H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/00 ,  H01L27/01 ,  H01L27/082 ,  H01L27/088 ,  H01L27/12 ,  H01L27/15 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L31/12 ,  H01L29/749

CPC分类号： H01L29/7317 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/7436 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.

摘要翻译： 复合集成电路器件包括半导体元件芯片，形成在半导体元件芯片上的定位引导件和通过定位引导件以自对准方式设置在半导体元件芯片上的预设位置的电子元件并安装在其上 。 还公开了具有锥形形状以减少击穿的横向薄膜装置。

公开(公告)号：US5463231A

公开(公告)日：1995-10-31

申请号：US353385

申请日：1994-12-02

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

IPC分类号： H01L27/06 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L27/0617 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.