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公开(公告)号:US20240389232A1
公开(公告)日:2024-11-21
申请号:US18220548
申请日:2023-07-11
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor: Chun Hung KUO , Kuo-Ching CHEN , Yu-Cheng HUANG , Yu-Hua CHEN
Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.
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公开(公告)号:US20190373713A1
公开(公告)日:2019-12-05
申请号:US16543609
申请日:2019-08-18
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang TSENG , Kai-Ming YANG , Pu-Ju LIN , Cheng-Ta KO , Yu-Hua CHEN
Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.
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公开(公告)号:US20250040051A1
公开(公告)日:2025-01-30
申请号:US18236280
申请日:2023-08-21
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor: Chun Hung KUO , Kuo-Ching CHEN , Yu-Cheng HUANG , Yu-Hua CHEN
Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.
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公开(公告)号:US20190239362A1
公开(公告)日:2019-08-01
申请号:US16379816
申请日:2019-04-10
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Cheng-Ta KO , John Hon-Shing LAU , Yu-Hua CHEN , Tzyy-Jang TSENG
IPC: H05K3/40 , H05K1/14 , H05K1/11 , H01L23/14 , H01L23/15 , H01L23/498 , H01L21/48 , H01L21/768 , H05K1/18
CPC classification number: H05K3/4038 , H01L21/4846 , H01L21/76898 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/014 , H01L2924/15311 , H05K1/11 , H05K1/112 , H05K1/142 , H05K1/183 , H05K2201/10674 , Y10T29/4913 , Y10T29/49146 , Y10T29/49165
Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
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公开(公告)号:US20220375919A1
公开(公告)日:2022-11-24
申请号:US17818006
申请日:2022-08-08
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Cheng-Ta KO , John Hon-Shing LAU , Yu-Hua CHEN , Tzyy-Jang TSENG
IPC: H01L25/00 , H01L21/48 , H01L23/538 , H01L23/00
Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.
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公开(公告)号:US20190139907A1
公开(公告)日:2019-05-09
申请号:US16240806
申请日:2019-01-07
Applicant: Unimicron Technology Corp.
Inventor: Pu-Ju LIN , Cheng-Ta KO , Yu-Hua CHEN , Tzyy-Jang TSENG , Ra-Min TAIN
Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
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7.
公开(公告)号:US20180005931A1
公开(公告)日:2018-01-04
申请号:US15257897
申请日:2016-09-06
Applicant: Unimicron Technology Corp.
Inventor: Yu-Hua CHEN , Cheng-Ta KO
IPC: H01L23/498 , H01L21/48 , H01L23/00
CPC classification number: H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/562 , H05K3/4682 , H05K3/4688 , H05K2201/096 , H05K2201/10378
Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
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8.
公开(公告)号:US20170048973A1
公开(公告)日:2017-02-16
申请号:US14821819
申请日:2015-08-10
Applicant: Unimicron Technology Corp.
Inventor: Shih-Liang CHENG , Dyi-Chung HU , Yu-Hua CHEN
CPC classification number: H05K1/11 , H05K1/0298 , H05K1/182 , H05K3/0032 , H05K3/0035 , H05K3/007 , H05K3/0097 , H05K3/045 , H05K3/107 , H05K3/205 , H05K3/421 , H05K2201/0195 , H05K2203/025 , H05K2203/107 , H05K2203/1476
Abstract: A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.
Abstract translation: 提供一种制造电路板结构的方法。 首先,在载体上形成第一电路层。 然后,在载体和第一电路层上形成第一电介质层。 此后,在第一电介质层中形成至少一个第一孔以暴露第一电路层的一部分。 然后,在第一电介质层和第一电路层上形成第二电介质层。 此后,在第二电介质层中形成至少一个沟槽和至少一个第二孔,其中沟槽露出第一电介质层的一部分,并且第二孔露出第一电路层的部分。 第二孔设置在第一孔中。 然后,形成金属层以填充沟槽和第二孔。
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公开(公告)号:US20240381533A1
公开(公告)日:2024-11-14
申请号:US18205240
申请日:2023-06-02
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor: Chun Hung KUO , Kuo-Ching CHEN , Yu-Cheng HUANG , Yu-Hua CHEN
Abstract: A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.
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公开(公告)号:US20210159191A1
公开(公告)日:2021-05-27
申请号:US17170736
申请日:2021-02-08
Applicant: Unimicron Technology Corp.
Inventor: Pu-Ju LIN , Cheng-Ta KO , Yu-Hua CHEN , Tzyy-Jang TSENG , Ra-Min TAIN
Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
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