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公开(公告)号：US09705173B2
公开(公告)日：2017-07-11
申请号：US14602290
申请日：2015-01-22
发明人： Tzung-Lin Li , Chien-Yi Lee , Chieh-Pin Chang
CPC分类号： H01P3/003 , H01P3/006 , H01P3/026 , H01P7/086 , H01P11/001
摘要： A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern.
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公开(公告)号：US10062943B2
公开(公告)日：2018-08-28
申请号：US15261879
申请日：2016-09-10
发明人： Tzung-Lin Li
CPC分类号： H01P3/082 , H01P3/08 , H01P3/081 , H01P11/003
摘要： A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ILD) layer is formed on the ground patterns, contact plugs are formed in the ILD layer, a ground plate is formed on the ILD layer, and a signal line is formed on the ground plate. Preferably, the ground plate includes openings that are completely shielded by the ground patterns.
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公开(公告)号：US09331161B1
公开(公告)日：2016-05-03
申请号：US14554068
申请日：2014-11-26
发明人： Chi-Ju Lee , Yao-Chang Wang , Nien-Ting Ho , Chi-Mao Hsu , Kuan-Cheng Su , Main-Gwo Chen , Hsiao-Kwang Yang , Fang-Hong Yao , Sheng-Huei Dai , Tzung-Lin Li
IPC分类号： H01L21/02 , H01L29/423 , H01L29/49 , H01L29/51 , H01L21/28
CPC分类号： H01L29/42376 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02244 , H01L21/02255 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/78
摘要： The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.
摘要翻译： 本发明提供了形成在电介质层的沟槽中的金属栅极结构。 金属栅极结构包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括底部和侧部，其中底部的厚度和侧部的厚度之间的比率在2-5之间。沟槽填充有金属 层。 本发明还提供一种形成金属栅极结构的方法。
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公开(公告)号：US08912844B2
公开(公告)日：2014-12-16
申请号：US13647392
申请日：2012-10-09
发明人： Tzung-Lin Li , Chun-Chang Wu , Chih-Yu Tseng
IPC分类号： H03K5/00
CPC分类号： H01L28/40 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/64 , H01L25/0657 , H01L28/10 , H01L2224/48091 , H01L2225/06506 , H01L2225/06513 , H01L2225/06527 , H01L2225/06544 , H01L2225/06568 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.
摘要翻译： 本发明提供一种包括基板，第一TSV，电感器和电容器的半导体结构。 第一TSV设置在基板中并且具有第一信号。 电感器设置在基板中。 电容器电连接到电感器以形成LC电路以绕过来自第一信号的噪声。 本发明还提供一种降低半导体结构中的信号噪声的方法。
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公开(公告)号：US20160197391A1
公开(公告)日：2016-07-07
申请号：US14602290
申请日：2015-01-22
发明人： Tzung-Lin Li , Chien-Yi Lee , Chieh-Pin Chang
CPC分类号： H01P3/003 , H01P3/006 , H01P3/026 , H01P7/086 , H01P11/001
摘要： A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern.
摘要翻译： 波导结构包括信号线和两条静态线。 信号线在第一方向上设置在静态线之间。 静态线路和信号线彼此平行设置。 每个静态线包括第一导电图案，第二导电图案和第三导电图案。 第一导电图案和信号线设置在电介质层的相同平面上。 第一导电图案的厚度基本上等于信号线的厚度。 第二导电图案设置在第一导电图案上。 第一导电图案的宽度大于第一导电图案在第一方向上的宽度。 第三导电图案设置在第二导电图案上。 第三导电图案的宽度大于第二导电图案的宽度。
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公开(公告)号：US20190148356A1
公开(公告)日：2019-05-16
申请号：US16248615
申请日：2019-01-15
发明人： Sheng-Huei Dai , Tzung-Lin Li
IPC分类号： H01L27/02 , H01L29/66 , H01L29/861
摘要： A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.
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公开(公告)号：US10262986B2
公开(公告)日：2019-04-16
申请号：US15621772
申请日：2017-06-13
发明人： Sheng-Huei Dai , Tzung-Lin Li
摘要： A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.
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公开(公告)号：US20180076500A1
公开(公告)日：2018-03-15
申请号：US15261879
申请日：2016-09-10
发明人： Tzung-Lin Li
CPC分类号： H01P3/082 , H01P3/08 , H01P3/081 , H01P11/003
摘要： A method for fabricating microstrip line structure is disclosed. First, a substrate is provided, ground patterns are formed on the substrate, an interlayer dielectric (ILD) layer is formed on the ground patterns, contact plugs are formed in the ILD layer, a ground plate is formed on the ILD layer, and a signal line is formed on the ground plate. Preferably, the ground plate includes openings that are completely shielded by the ground patterns.
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公开(公告)号：US20140097890A1
公开(公告)日：2014-04-10
申请号：US13647392
申请日：2012-10-09
发明人： Tzung-Lin Li , Chun-Chang Wu , Chih-Yu Tseng
CPC分类号： H01L28/40 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/64 , H01L25/0657 , H01L28/10 , H01L2224/48091 , H01L2225/06506 , H01L2225/06513 , H01L2225/06527 , H01L2225/06544 , H01L2225/06568 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.
摘要翻译： 本发明提供一种包括基板，第一TSV，电感器和电容器的半导体结构。 第一TSV设置在基板中并且具有第一信号。 电感器设置在基板中。 电容器电连接到电感器以形成LC电路以绕过来自第一信号的噪声。 本发明还提供一种降低半导体结构中的信号噪声的方法。
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公开(公告)号：US20180358351A1
公开(公告)日：2018-12-13
申请号：US15621772
申请日：2017-06-13
发明人： Sheng-Huei Dai , Tzung-Lin Li
CPC分类号： H01L27/0255 , H01L27/0288 , H01L29/66136 , H01L29/66174 , H01L29/94
摘要： A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.
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