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    Semiconductor device including conductive lines with fine line width and method of fabricating the same
    2.
    发明授权
    Semiconductor device including conductive lines with fine line width and method of fabricating the same 有权
    包括具有细线宽度的导线的半导体器件及其制造方法

    公开(公告)号：US08164119B2

    公开(公告)日：2012-04-24

    申请号：US13014952

    申请日：2011-01-27

    申请人： Hyeoung-Won Seo ,  Byung-Hyug Roh ,  Seong-Goo Kim ,  Sang-Min Jeon

    发明人： Hyeoung-Won Seo ,  Byung-Hyug Roh ,  Seong-Goo Kim ,  Sang-Min Jeon

    IPC分类号： H01L27/10

    CPC分类号： H01L27/10897 ,  H01L21/743 ,  H01L27/105 ,  H01L27/10882

    摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.

    摘要翻译： 半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线， 导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07629215B2

    公开(公告)日：2009-12-08

    申请号：US12128682

    申请日：2008-05-29

    申请人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

    发明人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

    IPC分类号： H01L21/8238 ,  H01L31/062

    CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

    摘要翻译： 半导体器件包括第一栅极结构，第二栅极结构，第一覆盖层图案，第二覆盖层图案，第一间隔物，第二间隔物，第三间隔物以及具有第一杂质区和第二杂质区的衬底。 第一栅极结构以第一间距布置在衬底上。 第二栅极结构以大于第一间距的第二间距布置在衬底上。 第一覆盖层图案具有沿着第一栅极结构的侧面延伸的段和沿着衬底延伸的段。 第二覆盖层图案具有沿着第二栅极结构延伸的段和沿着衬底延伸的段。 第一间隔物和第二间隔物层叠在第二覆盖层图案上。 第三间隔物形成在第一覆盖层图案上。

    Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed
    4.
    发明授权
    Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed 有权
    使用金属氮化硅层的集成电路绝缘电极形成方法和如此形成的绝缘电极

    公开(公告)号：US06187676B1

    公开(公告)日：2001-02-13

    申请号：US09134848

    申请日：1998-08-14

    申请人： Min-Jung Kim ,  Sang-Cheol Lee ,  Byung-Hyug Roh

    发明人： Min-Jung Kim ,  Sang-Cheol Lee ,  Byung-Hyug Roh

    IPC分类号： H01L214763

    CPC分类号： H01L29/4933 ,  H01L21/28061 ,  H01L21/28105 ,  H01L29/4941 ,  H01L29/4983

    摘要： Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the metal silicide layer. The metal silicon nitride layer acts as a silicon protrusion-preventing layer on the metal silicide layer that prevents formation of silicon protrusions from the metal silicide layer during subsequent processing. Reliability and/or yield problems that are caused by undercutting of an insulation layer in an insulated electrode may also be reduced by forming on an integrated circuit substrate, an insulating layer, conductive layer on the insulating layer and a metal silicide layer on the conductive layer. The metal silicide layer and the conductive layer are selectively etched to define an insulated electrode including a sidewall while also undesirably undercutting the insulating layer relative to the conductive layer thereon to define an undercut region. A conformal silicon nitride layer is coated on the integrated circuit substrate, including on the sidewall and in the undercut region. The conformal silicon nitride layer plugs the undercut insulating layer with silicon nitride, to thereby reduce reliability and/or yield problems.

    摘要翻译： 通过在集成电路基板，绝缘层，绝缘层上的导电层和导电层上的金属硅化物层上首先形成绝缘电极，然后在金属硅化物层上形成金属氮化硅层。 金属硅氮化物层在金属硅化物层上起防硅层的作用，防止在随后的处理期间从金属硅化物层形成硅突起。 通过在集成电路基板，绝缘层，绝缘层上的导电层和导电层上的金属硅化物层上形成，还可以减少由绝缘电极中的绝缘层的底切引起的可靠性和/或屈服问题 。 选择性地蚀刻金属硅化物层和导电层以限定包括侧壁的绝缘电极，同时也不利地使绝缘层相对于其上的导电层底切以限定底切区域。 在集成电路基板上涂覆保形氮化硅层，包括在侧壁和底切区域上。 保形氮化硅层用氮化硅堵塞底切绝缘层，从而降低可靠性和/或屈服问题。

    Forming trench isolators in semiconductor devices
    5.
    发明授权
    Forming trench isolators in semiconductor devices 有权
    在半导体器件中形成沟槽隔离器

    公开(公告)号：US6087233A

    公开(公告)日：2000-07-11

    申请号：US329844

    申请日：1999-06-11

    申请人： Byung-Hyug Roh

    发明人： Byung-Hyug Roh

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/336

    CPC分类号： H01L21/76224

    摘要： A method for forming a trench isolator in a semiconductor substrate comprises: forming a mask layer on the substrate having a opening defining a trench formation region on the substrate; etching the semiconductor substrate through the opening in the mask to form a trench in the substrate; depositing a trench isolation material on the substrate to fill the trench with the isolation material and form a trench isolator in the substrate; planarization-etching the trench isolation material until a top surface of the mask layer is exposed; and, forming a thin protective layer on the surface of the semiconductor substrate. The thin protective layer prevents an edge dipping effect of the trench isolator during subsequent cleaning processes, and enables the planarization-etching to reduce the thickness of the mask layer to the minimum thickness possible, thereby reducing the stresses applied to the semiconductor substrate by the mask layer during subsequent high temperature annealing processes.

    摘要翻译： 在半导体衬底中形成沟槽隔离器的方法包括：在衬底上形成掩模层，该掩模层在衬底上具有限定沟槽形成区域的开口; 通过掩模中的开口蚀刻半导体衬底，以在衬底中形成沟槽; 在衬底上沉积沟槽隔离材料以用隔离材料填充沟槽并在衬底中形成沟槽隔离器; 平坦化蚀刻沟槽隔离材料，直到掩模层的顶表面露出; 并且在半导体衬底的表面上形成薄的保护层。 薄的保护层防止沟道隔离器在随后的清洁过程中的边缘浸渍效应，并且能够进行平面化蚀刻以将掩模层的厚度减小到可能的最小厚度，从而减少由掩模施加到半导体衬底的应力 在随后的高温退火过程中。

    SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME 有权
    具有精细线宽度的导电线的半导体器件及其制造方法

    公开(公告)号：US20080203587A1

    公开(公告)日：2008-08-28

    申请号：US11865738

    申请日：2007-10-02

    申请人： Hyeoung-Won Seo ,  Byung-Hyug Roh ,  Seong-Goo Kim ,  Sang-Min Jeon

    发明人： Hyeoung-Won Seo ,  Byung-Hyug Roh ,  Seong-Goo Kim ,  Sang-Min Jeon

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L27/10897 ,  H01L21/743 ,  H01L27/105 ,  H01L27/10882

    摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.

    摘要翻译： 半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线， 导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。