公开(公告)号：US20070120238A1

公开(公告)日：2007-05-31

申请号：US11668127

申请日：2007-01-29

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L23/02

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.

Abstract translation: 提供一种形成计算机系统和印刷电路板组件的方法，包括第一和第二半导体管芯和中间衬底。 中间衬底位于第一半导体管芯的第一有源表面和第二半导体管芯的第二有源表面之间，使得中间衬底的第一表面面向第一有源表面，并且使得中间衬底的第二表面面向 第二活跃表面。 中间基板的第二表面包括限定在其中的空腔。 中间衬底在其中限定通道。 第二半导体管芯固定在空腔内的中间基板的第二表面上，使得第二半导体管芯的导电接合焊盘与通道对准。

公开(公告)号：US20050106780A1

公开(公告)日：2005-05-19

申请号：US11013487

申请日：2004-12-16

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L21/44

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.

公开(公告)号：US06274930B1

公开(公告)日：2001-08-14

申请号：US09606480

申请日：2000-06-29

Applicant: Venkateshwaran Vaiyapuri ,  Jicheng Yang

Inventor： Venkateshwaran Vaiyapuri ,  Jicheng Yang

IPC: H01L2334

CPC classification number: H01L23/5389 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multi-chip module may be formed by wire bonding a first chip within a cavity in a multi-chip carrier. A second die may be positioned over the first die, elevated therefrom, using bump bonding. In some embodiments, only a single cavity is utilized and in other embodiments, multiple cavities may be utilized, one of which mounts a first chip and the other of which mounts a second chip. In some embodiments, the second chip may be a composite of two dice coupled back-to-back so that the lowermost die may be bump bonded to the carrier and the uppermost die, facing upwardly away from the carrier, may be wire bonded thereto.

公开(公告)号：US06869827B2

公开(公告)日：2005-03-22

申请号：US10229969

申请日：2002-08-28

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.

Abstract translation: 提供一种形成计算机系统和印刷电路板组件的方法，包括第一和第二半导体管芯和中间衬底。 中间衬底位于第一半导体管芯的第一有源表面和第二半导体管芯的第二有源表面之间，使得中间衬底的第一表面面向第一有源表面，并且使得中间衬底的第二表面面向 第二活跃表面。 中间基板的第二表面包括限定在其中的空腔。 中间衬底在其中限定通道。 第二半导体管芯固定在空腔内的中间基板的第二表面上，使得第二半导体管芯的导电接合焊盘与通道对准。

公开(公告)号：US06762079B2

公开(公告)日：2004-07-13

申请号：US10082392

申请日：2002-02-25

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L2144

CPC classification number: H01L24/06 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.

Abstract translation: 一种用于增加半导体管芯组件中的集成电路密度的方法和装置，具体地说，是一个双LOC半导体管芯组件。 第一和第二模具基本上对称地背面粘合到基底引线框架的相对侧上的管芯附着位置。 然后，每个具有多个引导指的第一和第二偏移引线框架在其相对侧上附接到基部引线框架，使得它们的引导指以悬臂方式分别延伸超过第一和第二裸片。 在每个引线指的引线端之间，在第一和第二晶片上的相应的焊盘之间形成引线键，以在它们之间进行电连接。 然后将组件封装在传递模制过程中，然后对堆叠的双LOC半导体组件进行修整和形成操作。

公开(公告)号：US06629425B2

公开(公告)日：2003-10-07

申请号：US09912631

申请日：2001-07-23

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: F25D2312

CPC classification number: F04B43/046 ,  F04B43/12 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.

公开(公告)号：US07107777B2

公开(公告)日：2006-09-19

申请号：US10639836

申请日：2003-08-12

Applicant: Venkateshwaran Vaiyapuri ,  Fred Fishburn

Inventor： Venkateshwaran Vaiyapuri ,  Fred Fishburn

IPC: F25D23/12 ,  H05K7/20

CPC classification number: F04B43/046 ,  F04B43/12 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.

公开(公告)号：US06541846B2

公开(公告)日：2003-04-01

申请号：US09767446

申请日：2001-01-23

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L23495

CPC classification number: H01L24/06 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus for increasing integrated circuit density in a semiconductor die assembly, and specifically, a dual LOC semiconductor die assembly. A first and a second die are substantially symmetrically back bonded to a die attach site on a opposing sides of a base lead frame. A first and a second offset lead frame, each having a plurality of lead fingers, are then attached to the base lead frame on opposing sides thereof so that their lead fingers respectively extend over the first and second dice in a cantilevered manner. Wire bonds are formed between lead ends of each of the lead fingers to corresponding bond pads on the first and second dice for electrical connection therebetween. The assembly is then encapsulated in a transfer molding process, after which the stacked dual LOC semiconductor assembly is subjected to a trim and form operation.

公开(公告)号：US06507107B2

公开(公告)日：2003-01-14

申请号：US09855731

申请日：2001-05-15

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L2313

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/642 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A computer system and a printed circuit board assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between a first active surface of the first semiconductor die and a second active surface of the second semiconductor die. The first semiconductor die is electrically coupled to the intermediate substrate. The intermediate substrate defines a passage there through The second semiconductor die is secured to the second surface of the intermediate substrate within a cavity in the second surface of the intermediate substrate such that the conductive bond pad of the second semiconductor die is aligned with the passage. The second semiconductor die is electrically coupled to the intermediate substrate by at least one conductive line extending from the second semiconductor die through the passage and to the first surface of the intermediate substrate.

Abstract translation: 提供了包括第一和第二半导体管芯和中间衬底的计算机系统和印刷电路板组件。 中间基板位于第一半导体管芯的第一有源表面和第二半导体管芯的第二有源表面之间。 第一半导体管芯电耦合到中间衬底。 中间基板在其上限定通道。第二半导体管芯在中间基板的第二表面的空腔内固定到中间基板的第二表面，使得第二半导体管芯的导电接合焊盘与通道对准。 第二半导体管芯通过至少一个从第二半导体管芯通过通道延伸到中间衬底的第一表面的导电线电耦合到中间衬底。

公开(公告)号：US06207467B1

公开(公告)日：2001-03-27

申请号：US09437595

申请日：1999-11-10

Applicant: Venkateshwaran Vaiyapuri ,  Jicheng Yang

Inventor： Venkateshwaran Vaiyapuri ,  Jicheng Yang

IPC: H01L2166

CPC classification number: H01L23/5389 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multi-chip module may be formed by wire bonding a first chip within a cavity in a multi-chip carrier. A second die may be positioned over the first die, elevated therefrom, using bump bonding. In some embodiments, only a single cavity is utilized and in other embodiments, multiple cavities may be utilized, one of which mounts a first chip and the other of which mounts a second chip. In some embodiments, the second chip may be a composite of two dice coupled back-to-back so that the lowermost die may be bump bonded to the carrier and the uppermost die, facing upwardly away from the carrier, may be wire bonded thereto.

Abstract translation: 可以通过将多芯片载体中的空腔内的第一芯片引线接合而形成多芯片模块。 可以使用凸块接合将第二模具定位在第一模具上方，从其上升高。 在一些实施例中，仅使用单个空腔，并且在其它实施例中，可以利用多个空腔，其中一个安装第一芯片，另一个安装第二芯片。 在一些实施例中，第二芯片可以是背对背耦合的两个芯片的复合材料，使得最下面的芯片可以凸起地结合到载体上，并且最上面的模具面向上远离载体可以被引线键合到其上。