公开(公告)号：US08435827B2

公开(公告)日：2013-05-07

申请号：US13348255

申请日：2012-01-11

申请人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

发明人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

IPC分类号： H01L21/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16 ,  H01L45/1608

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 牺牲金属设置在电化学活性电极和惰性电极之间。 牺牲金属具有比成丝金属更负的标准电极电位。

公开(公告)号：US08097874B2

公开(公告)日：2012-01-17

申请号：US12500899

申请日：2009-07-10

申请人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

发明人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

IPC分类号： H01L47/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16 ,  H01L45/1608

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 牺牲金属设置在电化学活性电极和惰性电极之间。 牺牲金属具有比成丝金属更负的标准电极电位。

公开(公告)号：US20120104349A1

公开(公告)日：2012-05-03

申请号：US13348255

申请日：2012-01-11

申请人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

发明人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

IPC分类号： H01L45/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16 ,  H01L45/1608

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 牺牲金属设置在电化学活性电极和惰性电极之间。 牺牲金属具有比成丝金属更负的标准电极电位。

公开(公告)号：US20100108978A1

公开(公告)日：2010-05-06

申请号：US12500899

申请日：2009-07-10

申请人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

发明人： Venkatram Venkatasamy ,  Ming Sun ,  Dadi Setiadi

IPC分类号： H01L47/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/16 ,  H01L45/1608

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 牺牲金属设置在电化学活性电极和惰性电极之间。 牺牲金属具有比成丝金属更负的标准电极电位

公开(公告)号：US08617952B2

公开(公告)日：2013-12-31

申请号：US12891966

申请日：2010-09-28

申请人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

发明人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC分类号： H01L21/336

CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

公开(公告)号：US08460794B2

公开(公告)日：2013-06-11

申请号：US12500892

申请日：2009-07-10

申请人： Jun Zheng ,  Dadi Setiadi

发明人： Jun Zheng ,  Dadi Setiadi

IPC分类号： B32B9/00 ,  B32B33/00

CPC分类号： B32B7/005 ,  B23K31/02 ,  H01L21/187 ,  H01L23/29 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16111 ,  H01L2224/16147 ,  H01L2224/81002 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81805 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  Y10T428/24562 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/31504 ,  Y10T428/31678 ,  H01L2224/81001 ,  H01L2224/05552

摘要： A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

摘要翻译： 晶片制品包括衬底，设置在衬底上的两个或更多个亲水区域，围绕亲水区域的疏水区域以及设置在衬底上的共晶接合材料。 公开了包括具有互补的亲水区域和共晶接合材料的两个晶片的晶片装置，并且公开了形成接合晶片制品的方法。

公开(公告)号：US08183126B2

公开(公告)日：2012-05-22

申请号：US12502178

申请日：2009-07-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L21/30

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US08158964B2

公开(公告)日：2012-04-17

申请号：US12502221

申请日：2009-07-13

申请人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

发明人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

IPC分类号： H01L29/02 ,  H01L29/47

CPC分类号： H01L27/0814 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/872 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147

摘要： A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

公开(公告)号：US20120074488A1

公开(公告)日：2012-03-29

申请号：US12891966

申请日：2010-09-28

申请人： Young Pil Kim ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

发明人： Young Pil Kim ,  Hyung-Kyu Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

公开(公告)号：US20110006276A1

公开(公告)日：2011-01-13

申请号：US12502221

申请日：2009-07-13

申请人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

发明人： Young Pil Kim ,  Nurul Amin ,  Dadi Setiadi ,  Venugopalan Vaithyanathan ,  Wei Tian ,  Insik Jin

IPC分类号： H01L45/00 ,  H01L29/868 ,  H01L21/30

CPC分类号： H01L27/0814 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/872 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147

摘要： A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

摘要翻译： 一种开关元件，包括第一半导体层，所述第一半导体层具有第一部分和第二部分; 第二半导体层，所述第二半导体层具有第一部分和第二部分; 设置在所述第一半导体层和所述第二半导体层之间的绝缘层; 与所述第一半导体层的所述第一部分接触的第一金属触点，形成第一结，并与所述第二半导体层的所述第一部分接触形成第二结; 第二金属触点与第一半导体层的第二部分接触形成第三结，并与第二半导体层的第二部分接触形成第四结，其中第一结和第四结是肖特基接触， 第二结和第三结是欧姆接触。