公开(公告)号：US20050017365A1

公开(公告)日：2005-01-27

申请号：US10919773

申请日：2004-08-16

申请人： Vijayakumar RamachandraRao ,  David Gracias

发明人： Vijayakumar RamachandraRao ,  David Gracias

IPC分类号： B32B3/00 ,  H01L21/302 ,  H01L21/31 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24802 ,  Y10T428/256

摘要： Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.

摘要翻译： 与多孔低k电介质材料相关的加工问题通常是严重的。 在特征蚀刻，灰化和引发步骤期间，低k材料暴露于等离子体具有有害的后果。 对于多孔的硅基低k电介质材料，等离子体消耗了表面有机基团，提高了材料的介电常数。 在最坏的情况下，在通孔 - 第一铜双镶嵌集成方案中的抗反射涂层的湿蚀刻去除期间损坏的电介质被破坏。 通过在不同的蚀刻和清洁阶段将电介质暴露于硅烷偶联剂来解决这个问题。 与硅烷偶联剂的化学反应都补充电介质表面有机基团并相对于抗反射涂层的表面钝化电介质表面。

公开(公告)号：US20050190020A1

公开(公告)日：2005-09-01

申请号：US11103394

申请日：2005-04-11

申请人： Kevin O'Brien ,  David Gracias

发明人： Kevin O'Brien ,  David Gracias

IPC分类号： H01L21/768 ,  H01L23/532 ,  H05K1/02 ,  H01P3/08

CPC分类号： H01L23/5329 ,  H01L21/76829 ,  H01L2924/0002 ,  H05K1/024 ,  H01L2924/00

摘要： By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in different directions. As integrated circuits scale, importance of line to line capacitance in one plane increases. Thus, in some embodiments, the dielectric constant of the oriented dielectric may be lower in the plane that controls line to line capacitance.

公开(公告)号：US07375425B2

公开(公告)日：2008-05-20

申请号：US11327944

申请日：2006-01-09

申请人： David Gracias

发明人： David Gracias

IPC分类号： H01L23/34 ,  H01L21/48

CPC分类号： H01L24/81 ,  H01L25/50 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： Fluidic self-assembly may be utilized to form a stack of two integrated circuits. The integrated circuits may include surface mount electrical connections and surface features that control the alignment between the integrated circuits. In particular, the contacts may be provided on one side of each integrated circuit and surface features may cause the integrated circuits to align with one another in an immersion fluid. The aligned circuits may join to form physical and electrical connections. The resulting structure may be a stack of two integrated circuits electrically coupled to one another.

摘要翻译： 流体自组装可用于形成两个集成电路的堆叠。 集成电路可以包括表面贴装电连接和控制集成电路之间的对准的表面特征。 特别地，触点可以设置在每个集成电路的一侧上，并且表面特征可以导致集成电路在浸没流体中彼此对准。 对准的电路可以连接以形成物理和电连接。 所得到的结构可以是彼此电耦合的两个集成电路的堆叠。

公开(公告)号：US20070020310A1

公开(公告)日：2007-01-25

申请号：US11491829

申请日：2006-07-24

申请人： David Gracias ,  Barjor Gimi ,  Zaver Bhujwalla

发明人： David Gracias ,  Barjor Gimi ,  Zaver Bhujwalla

IPC分类号： A61B5/05 ,  A61K9/22

CPC分类号： A61K9/0024 ,  A61B5/055 ,  A61K9/0097 ,  A61K9/5115 ,  A61K9/5138 ,  A61K9/5192 ,  A61K49/18 ,  B82Y5/00 ,  Y10S977/70 ,  Y10S977/902 ,  Y10S977/904 ,  Y10S977/905 ,  Y10S977/906 ,  Y10S977/915

摘要： The present invention relates to a nanoscale or microscale container for encapsulation and delivery of materials or substances, including, but not limited to, cells, drugs, tissue, gels and polymers contained within the container, with subsequent release of the therapeutic materials in situ, methods of fabricating the container by folding a 2D precursor into the 3D container, and the use of the container in in-vivo or in-vitro applications. The container can be in any polyhedral shape and its surfaces can have either no perforations or nano/microscale perforations. The container is coated with a biocompatible metal, e.g. gold, or polymer, e.g. parylene, layer and the surfaces and hinges of the container are made of any metal or polymer combinations.

摘要翻译： 本发明涉及用于包封和递送材料或物质的纳米尺度或微尺寸容器，包括但不限于容纳在容器内的细胞，药物，组织，凝胶和聚合物，以及原位释放治疗材料， 通过将2D前体折叠到3D容器中来制造容器的方法，以及在体内或体外应用中使用该容器。 容器可以是任何多面体形状，并且其表面可以不具有穿孔或纳米/微孔穿孔。 容器用生物相容性金属涂覆，例如 金或聚合物，例如 聚对二甲苯，层和容器的表面和铰链由任何金属或聚合物组合制成。

公开(公告)号：US06927180B2

公开(公告)日：2005-08-09

申请号：US10306066

申请日：2002-11-27

申请人： Kevin O'Brien ,  David Gracias

发明人： Kevin O'Brien ,  David Gracias

IPC分类号： H01L21/768 ,  H01L23/532 ,  H05K1/02 ,  H01L21/31

CPC分类号： H01L23/5329 ,  H01L21/76829 ,  H01L2924/0002 ,  H05K1/024 ,  H01L2924/00

摘要： By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in different directions. As integrated circuits scale, importance of line to line capacitance in one plane increases. Thus, in some embodiments, the dielectric constant of the oriented dielectric may be lower in the plane that controls line to line capacitance.

摘要翻译： 通过将电介质暴露于强电场，各向异性特性可能被引入到电介质中。 这可能导致电介质在不同方向上具有不同的介电常数。 随着集成电路规模的扩大，一个平面线对线电容的重​​要性增加。 因此，在一些实施例中，取向电介质的介电常数可以在控制线对电容的平面中较低。

公开(公告)号：US20060191125A1

公开(公告)日：2006-08-31

申请号：US11352923

申请日：2006-02-13

申请人： David Gracias ,  Joe Tien ,  George Whitesides

发明人： David Gracias ,  Joe Tien ,  George Whitesides

IPC分类号： H01L21/00

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L25/50 ,  H01L2224/95122 ,  H01L2224/95144 ,  H01L2224/95145 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/12041 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49208 ,  Y10T29/4921

摘要： Techniques for self assembly of macro-scale objects, optionally defining electrical circuitry, are described, as well as articles formed by self assembly. Components can be joined, during self-assembly by minimization of free energy, capillary attraction, or a combination.

公开(公告)号：US07018867B2

公开(公告)日：2006-03-28

申请号：US10360042

申请日：2003-02-06

申请人： David Gracias

发明人： David Gracias

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  H01L25/50 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： Fluidic self-assembly may be utilized to form a stack of two integrated circuits. The integrated circuits may include surface mount electrical connections and surface features that control the alignment between the integrated circuits. In particular, the contacts may be provided on one side of each integrated circuit and surface features may cause the integrated circuits to align with one another in an immersion fluid. The aligned circuits may join to form physical and electrical connections. The resulting structure may be a stack of two integrated circuits electrically coupled to one another.

公开(公告)号：US20050236714A1

公开(公告)日：2005-10-27

申请号：US11170322

申请日：2005-06-28

申请人： Jihperng Leu ,  Grant Kloster ,  David Gracias ,  Lee Rockford ,  Peter Moon ,  Chris Barns

发明人： Jihperng Leu ,  Grant Kloster ,  David Gracias ,  Lee Rockford ,  Peter Moon ,  Chris Barns

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/7682

摘要： An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

摘要翻译： 公开了一种层间电介质结构及其制造方法。 形成初始包含多孔基质和致孔剂的复合介电层。 在其它处理处理之后，致孔剂从多孔基体的至少一部分分解和除去，留下由多孔基质定义的空隙，其中先前由致孔剂占据的区域。 所得结构由于孔隙率和包含多孔基质和致孔剂的材料而具有期望的低k值。 复合介电层可以与具有不同孔隙率，尺寸和材料性质的其它电介质层一起使用，以提供不同的机械和电气性能轮廓。

公开(公告)号：US20050091931A1

公开(公告)日：2005-05-05

申请号：US10997607

申请日：2004-11-23

申请人： David Gracias

发明人： David Gracias

IPC分类号： B24D3/02 ,  C09C1/68 ,  C09K3/14 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate monolayers to prevent the electromigration and surface diffusion of copper atoms while minimizing the resistance of the interconnect lines. Self assembled thiolate monolayers are used to cap the copper interconnect lines and chemically hold the copper atoms at the top of the lines in place, thus preventing surface diffusion. The use of self assembled thiolate monolayers minimizes the resistance of copper interconnect lines because only a single monolayer of approximately 10 Å and 20 Å in thickness is used.

公开(公告)号：US20060118971A1

公开(公告)日：2006-06-08

申请号：US11327944

申请日：2006-01-09

申请人： David Gracias

发明人： David Gracias

IPC分类号： H01L23/48

CPC分类号： H01L24/81 ,  H01L25/50 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： Fluidic self-assembly may be utilized to form a stack of two integrated circuits. The integrated circuits may include surface mount electrical connections and surface features that control the alignment between the integrated circuits. In particular, the contacts may be provided on one side of each integrated circuit and surface features may cause the integrated circuits to align with one another in an immersion fluid. The aligned circuits may join to form physical and electrical connections. The resulting structure may be a stack of two integrated circuits electrically coupled to one another.

摘要翻译： 流体自组装可用于形成两个集成电路的堆叠。 集成电路可以包括表面贴装电连接和控制集成电路之间的对准的表面特征。 特别地，触点可以设置在每个集成电路的一侧上，并且表面特征可以导致集成电路在浸没流体中彼此对准。 对准的电路可以连接以形成物理和电连接。 所得到的结构可以是彼此电耦合的两个集成电路的堆叠。