公开(公告)号：US09275941B2

公开(公告)日：2016-03-01

申请号：US14367788

申请日：2012-08-31

申请人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

发明人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

IPC分类号： H01L21/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49524 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0311 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/43847 ,  H01L2224/4502 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85181 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/43

摘要： The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

摘要翻译： 本发明公开了一种四边形无铅封装及其制造方法。 四边形无铅封装包括由载体凹坑和布置在载体凹坑周围的三个引线组成的引线框载体，其中三个引线圈分别由相互断开的多个引线组成; IC芯片粘附在载体坑中; 并在所有的引线上镀上一个内引铅化学镍和斑铜矿镀层; 内部引线化学镍和长磷石镀层沿与IC芯片相同的方向排列; IC芯片通过接合线与内引线化学镍和卟啉镀层连接; 和IC芯片，镀有内引线化学镀镍和钯金属层的所有引线的端部和接合线全部封装在塑料封装中。 通过以下步骤制造四边形扁平无铅封装：薄片化和刻划晶片; 制造引线框架; 加载芯片; 执行压焊和塑料包装; 执行后固化; 打印; 电镀; 分离引线; 分离产品; 和测试/编织。 根据封装，解决了现有普通四边形无铅封装单面封装时引线少，焊丝长，焊接成本高，应用频率有限的问题。

公开(公告)号：US20150102476A1

公开(公告)日：2015-04-16

申请号：US14367788

申请日：2012-08-31

申请人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

发明人： Wenhui Zhu ,  Wei Mu ,  Zhaoming Xu ,  Xiaowei Guo

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49524 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0311 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/43847 ,  H01L2224/4502 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85181 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/43

摘要： The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

摘要翻译： 本发明公开了一种四边形无铅封装及其制造方法。 四边形无铅封装包括由载体凹坑和布置在载体凹坑周围的三个引线组成的引线框载体，其中三个引线圈分别由相互断开的多个引线组成; IC芯片粘附在载体坑中; 并在所有的引线上镀上一个内引铅化学镍和斑铜矿镀层; 内部引线化学镍和长磷石镀层沿与IC芯片相同的方向排列; IC芯片通过接合线与内引线化学镍和卟啉镀层连接; 和IC芯片，镀有内引线化学镀镍和钯金属层的所有引线的端部和接合线全部封装在塑料封装中。 通过以下步骤制造四边形扁平无铅封装：薄片化和刻划晶片; 制造引线框架; 加载芯片; 执行压焊和塑料包装; 执行后固化; 打印; 电镀; 分离引线; 分离产品; 和测试/编织。 根据封装，解决了现有普通四边形无铅封装单面封装时引线少，焊丝长，焊接成本高，应用频率有限的问题。

公开(公告)号：US20130223018A1

公开(公告)日：2013-08-29

申请号：US13883672

申请日：2010-12-30

申请人： Jianyou Xie ,  Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xin Chen

发明人： Jianyou Xie ,  Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xin Chen

IPC分类号： H05K1/18 ,  H05K3/00

CPC分类号： H05K1/181 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49855 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K3/00 ,  Y10T29/49146 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A high-density Subscriber Identity Module (SIM) card package and a production method thereof are provided. The SIM card package includes a substrate, an Integrated Circuit (IC) chip, a bonding wire, and a mold cap. The substrate is a two-layer, a four-layer, a six-layer or an eight-layer high-density interlinked and packaged organic laminated substrate that is manufactured through an etching-back process, and a passive device and a crystal oscillator are provided on the organic laminated substrate. Two IC chips are provided side by side, or one of the IC chips is stacked with a third IC chip, the third IC chip being respectively connected to the organic laminated substrate and the IC chip under the third IC chip by the bonding wire. The IC chip, the passive device, and the crystal oscillator are adhered to the organic laminated substrate, and the IC chip is connected to the organic laminated substrate by the bonding wire; the height and the shape of a wire arc is controlled, an injection procedure is controller by using multi-stage injection model software; then, marking and cutting are performed to obtain the SIM card package. The dimension of the package of the present invention is 12 mm×18 mm×0.63 mm, devices of multiple kinds are molded, thereby meeting use requirements for multiple functions.

摘要翻译： 提供了一种高密度用户识别模块（SIM）卡包及其制作方法。 SIM卡封装包括基板，集成电路（IC）芯片，接合线和模具盖。 基板是通过蚀刻回复工艺制造的双层，四层，六层或八层高密度互连和封装的有机层叠基板，无源器件和晶体振荡器是 设置在有机层叠基板上。 并排设置两个IC芯片，或者将IC芯片中的一个与第三IC芯片堆叠，第三IC芯片通过接合线分别连接到有机层叠基板和第三IC芯片下方的IC芯片。 IC芯片，无源器件和晶体振荡器粘附到有机层叠基板上，IC芯片通过接合线连接到有机层叠基板; 控制线弧的高度和形状，注射程序是使用多级注射模型软件的控制器; 然后执行标记和切割以获得SIM卡封装。 本发明的包装尺寸为12mm×18mm×0.63mm，成型为多种装置，满足多种功能的使用要求。

公开(公告)号：US20130334686A1

公开(公告)日：2013-12-19

申请号：US13883936

申请日：2010-12-30

申请人： Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xinjun Wang

发明人： Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xinjun Wang

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at a front side of the package, and is designed to be an exposed multi-row approximate square-shaped circular gold-plated contacts at a back side; the IC chip is provided on the inner pin, the inner pin is adhered to the IC chip with an adhesive film sheet, the pad on the IC chip is connected to the inner pin by the bonding wire, and the mold cap encircles the adhesive film sheet, the IC chip, the bonding wire, and edges of the inner pin, so as to form a whole circuit. The present invention adopts approximate square-shaped spherical array contacts, thereby having a simple and flexible structure, and achieving a desirable heat-dissipation effect. A cooper lead frame (L/F) has a high yield, and reduces the material cost. The L/F is used to replace a ceramic substrate, PCB substrate, or BT substrate, thereby saving the complicated layout design, shortening the designing and manufacturing cycle, accelerating the trial production course, and enabling the product to be early listed to obtain market opportunities.

摘要翻译： 提供了一种无载波地栅阵列（LGA）集成电路（IC）芯片封装及其制备方法。 IC芯片封装包括：内部引脚，IC芯片，焊盘，接合线和模具盖。 内销被设计为在包装前侧的多排矩阵形式，并被设计为背面暴露的多排近似方形圆形镀金触点; IC芯片设置在内部引脚上，内部引脚用粘合膜片粘合到IC芯片上，IC芯片上的焊盘通过接合线连接到内部引脚，并且模具盖环绕粘合膜 片，IC芯片，接合线和内销的边缘，以形成整个电路。 本发明采用近似的方形球形阵列触点，从而具有简单而灵活的结构，并达到理想的散热效果。 铜杆引线框架（L / F）具有高产量，降低了材料成本。 L / F用于替代陶瓷基板，PCB基板或BT基板，从而节省复杂的布局设计，缩短设计和制造周期，加快试生产过程，使产品能够早日上市获得市场 机会。

公开(公告)号：US09210813B2

公开(公告)日：2015-12-08

申请号：US13883672

申请日：2010-12-30

申请人： Jianyou Xie ,  Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xin Chen

发明人： Jianyou Xie ,  Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xin Chen

IPC分类号： H05K3/30 ,  H05K1/18 ,  H01L23/00 ,  H05K3/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H05K1/181 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49855 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K3/00 ,  Y10T29/49146 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A high-density Subscriber Identity Module (SIM) card package and a production method thereof are provided. The SIM card package includes a substrate, an Integrated Circuit (IC) chip, a bonding wire, and a mold cap. The substrate is a two-layer, a four-layer, a six-layer or an eight-layer high-density interlinked and packaged organic laminated substrate that is manufactured through an etching-back process, and a passive device and a crystal oscillator are provided on the organic laminated substrate. Two IC chips are provided side by side, or one of the IC chips is stacked with a third IC chip, the third IC chip being respectively connected to the organic laminated substrate and the IC chip under the third IC chip by the bonding wire. The IC chip, the passive device, and the crystal oscillator are adhered to the organic laminated substrate.

摘要翻译： 提供了一种高密度用户识别模块（SIM）卡包及其制作方法。 SIM卡封装包括基板，集成电路（IC）芯片，接合线和模具盖。 基板是通过蚀刻回复工艺制造的双层，四层，六层或八层高密度互连和封装的有机层叠基板，无源器件和晶体振荡器是 设置在有机层叠基板上。 并排设置两个IC芯片，或者将IC芯片中的一个与第三IC芯片堆叠，第三IC芯片通过接合线分别连接到有机层叠基板和第三IC芯片下方的IC芯片。 将IC芯片，无源器件和晶体振荡器粘附到有机层叠基板上。

公开(公告)号：US09136231B2

公开(公告)日：2015-09-15

申请号：US13883936

申请日：2010-12-30

申请人： Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xinjun Wang

发明人： Xiaowei Guo ,  Wenhai He ,  Wei Mu ,  Xinjun Wang

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at a front side of the package, and is designed to be an exposed multi-row approximate square-shaped circular gold-plated contacts at a back side; the IC chip is provided on the inner pin, the inner pin is adhered to the IC chip with an adhesive film sheet, the pad on the IC chip is connected to the inner pin by the bonding wire, and the mold cap encircles the adhesive film sheet, the IC chip, the bonding wire, and edges of the inner pin, so as to form a whole circuit. The present invention adopts approximate square-shaped spherical array contacts, thereby having a simple and flexible structure, and achieving a desirable heat-dissipation effect. A cooper lead frame (L/F) has a high yield, and reduces the material cost. The L/F is used to replace a ceramic substrate, PCB substrate, or BT substrate, thereby saving the complicated layout design, shortening the designing and manufacturing cycle, accelerating the trial production course, and enabling the product to be early listed to obtain market opportunities.

摘要翻译： 提供了一种无载波地栅阵列（LGA）集成电路（IC）芯片封装及其制备方法。 IC芯片封装包括：内部引脚，IC芯片，焊盘，接合线和模具盖。 内销被设计为在包装前侧的多排矩阵形式，并被设计为背面暴露的多排近似方形圆形镀金触点; IC芯片设置在内部引脚上，内部引脚用粘合膜片粘合到IC芯片上，IC芯片上的焊盘通过接合线连接到内部引脚，并且模具盖环绕粘合膜 片，IC芯片，接合线和内销的边缘，以形成整个电路。 本发明采用近似的方形球形阵列触点，从而具有简单而灵活的结构，并达到理想的散热效果。 铜杆引线框架（L / F）具有高产量，降低了材料成本。 L / F用于替代陶瓷基板，PCB基板或BT基板，从而节省复杂的布局设计，缩短设计和制造周期，加快试生产过程，使产品能够早日上市获得市场 机会。

公开(公告)号：US09349615B2

公开(公告)日：2016-05-24

申请号：US13883143

申请日：2010-12-30

申请人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

发明人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

IPC分类号： H01L29/00 ,  H01L21/56 ,  H01L25/065 ,  H01L27/04 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/04 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC).

摘要翻译： 提供一种系统级封装（SiP）系统集成电路（IC）芯片封装及其制造方法。 封装包括衬底，无源器件和两个IC芯片设置在衬底上，粘合膜设置在两个IC芯片和衬底之间，IC芯片通过接合线连接到衬底上的第一焊盘， 并且基板被模具盖覆盖。 第三IC芯片可以进一步设置在一个IC芯片上，并且第三IC芯片分别通过接合线连接到第三IC芯片下面的第一焊盘和IC芯片。 使用采用表面贴装技术（SMT）PAD开窗方式的基板，在基板上进行芯片安装，并且基板进行回流焊接，清洗，芯片接合，等离子体清洗，接合，标记，切割和封装， 从而制造SiP系统集成IC芯片封装。 本发明的封装集成了不同类型的器件，具有完整的系统功能，可以作为芯片（SoC）进一步开发的中间阶段。

公开(公告)号：US08538960B2

公开(公告)日：2013-09-17

申请号：US13204631

申请日：2011-08-05

申请人： Sandy Wong ,  Wei Mu ,  Jun Yin ,  Rahul Nair ,  Simon King ,  Srinivasan Badrinarayanan ,  Xavier Legros ,  Michael Ching ,  Kevin Haas ,  Shubha Nabar

发明人： Sandy Wong ,  Wei Mu ,  Jun Yin ,  Rahul Nair ,  Simon King ,  Srinivasan Badrinarayanan ,  Xavier Legros ,  Michael Ching ,  Kevin Haas ,  Shubha Nabar

IPC分类号： G06F17/30

CPC分类号： G06F17/3053 ,  G06F17/30861 ,  G06F17/30867

摘要： Search results may include both objective results and person results. In one example, a search query is evaluated to determine whether it is the type of query that a user might want to ask to a friend. If the query is of such a type, then the search engine may examine a social graph to determine which friends of the user who entered the query may have information that is relevant to answering the query. If such friends exist, then the friends may be displayed along with objective search results, along with an explanation of each friend's relevance to the query. Clicking on a person in the results may cause a conversation to be initiated with that person, thereby allowing the user who entered the query to ask his or her friend about the subject of the query.

摘要翻译： 搜索结果可能包括客观结果和个人结果。 在一个示例中，评估搜索查询以确定用户可能想要向朋友询问的查询的类型。 如果查询是类似的，则搜索引擎可以检查社交图来确定输入查询的用户的哪些朋友可能具有与回答查询相关的信息。 如果存在这样的朋友，那么朋友可以与客观的搜索结果一起显示，以及每个朋友对查询的相关性的解释。 点击结果中的某人可能会导致与该人发起对话，从而允许输入查询的用户向其或朋友询问查询的主题。

公开(公告)号：US06459008B1

公开(公告)日：2002-10-01

申请号：US09599612

申请日：2000-06-23

申请人： Wei Dai ,  Jing Zhu ,  Helong Li ,  Yanlai Guo ,  Wei Mu ,  Hui Peng ,  Xin Chen

发明人： Wei Dai ,  Jing Zhu ,  Helong Li ,  Yanlai Guo ,  Wei Mu ,  Hui Peng ,  Xin Chen

IPC分类号： C07C402

CPC分类号： C10G45/40 ,  B01J23/6447

摘要： A selective hydrogenation catalyst system, and a process for its preparation and its use. The catalyst system of the invention comprises a support material, a Pd-containing catalyst component and a Bi-containing cocatalyst component. The catalyst system of the invention is manufactured by impregnating the support material simultaneously or separately with Pd-containing solution, Bi-containing solution or/and one or more other cocatalyst solutions, and then drying and calcining. The activity and selectivity of the catalyst system of the invention, in selective hydrogenation of acetylenic and diolefmic compounds in hydrocarbon feeds, are significantly improved, while the green oil formation and carbon deposit on the catalyst reduced, and the service life increased and production costs decreased.

摘要翻译： 选择性氢化催化剂体系及其制备方法及其应用。 本发明的催化剂体系包括载体材料，含Pd催化剂组分和含Bi助催化剂组分。 本发明的催化剂体系是通过与含Pd溶液，含Bi的溶液或一种或多种其它助催化剂溶液同时或分开地浸渍载体材料，然后干燥和煅烧来制造的。 本发明的催化剂体系在烃类进料中炔属和二烯化合物的选择性氢化中的活性和选择性得到显着提高，而催化剂上的绿色油形成和碳沉积减少，使用寿命增加，生产成本降低 。

公开(公告)号：US20130214386A1

公开(公告)日：2013-08-22

申请号：US13883143

申请日：2010-12-30

申请人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

发明人： Jianyou Xie ,  Xizhou Li ,  Wei Mu ,  Yongzhong Wang ,  Haidong Wei

IPC分类号： H01L21/56 ,  H01L27/04

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/04 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC).

摘要翻译： 提供一种系统级封装（SiP）系统集成电路（IC）芯片封装及其制造方法。 封装包括衬底，无源器件和两个IC芯片设置在衬底上，粘合膜设置在两个IC芯片和衬底之间，IC芯片通过接合线连接到衬底上的第一焊盘， 并且基板被模具盖覆盖。 第三IC芯片可以进一步设置在一个IC芯片上，并且第三IC芯片分别通过接合线连接到第三IC芯片下面的第一焊盘和IC芯片。 使用采用表面贴装技术（SMT）PAD开窗方式的基板，在基板上进行芯片安装，并且基板进行回流焊接，清洗，芯片接合，等离子体清洗，接合，标记，切割和封装， 从而制造SiP系统集成IC芯片封装。 本发明的封装集成了不同类型的器件，具有完整的系统功能，可以作为芯片（SoC）进一步开发的中间阶段。