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公开(公告)号：US4096584A
公开(公告)日：1978-06-20
申请号：US764031
申请日：1977-01-31
IPC分类号： G11C11/412 , G11C11/417 , G11C11/40
CPC分类号： G11C11/412 , G11C11/417
摘要： An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. "Zero" threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.
摘要翻译： 描述了具有掉电模式的集成电路，金属氧化物半导体（MOS）静态随机存取存储器（RAM）。 在存储器中使用的双稳态存储器单元包括用作负载的低导电率，耗尽型晶体管。 “零”阈值电压器件用于低体效衬底，以允许存储器中许多电路的掉电而不影响电路性能。 描述采用这些零阈值装置的几个电路。
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2.发明授权Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor 失效用多晶硅多晶硅电阻器形成多晶硅层之间的接触区域的工艺
公开(公告)号：US4178674A
公开(公告)日：1979-12-18
申请号：US890139
申请日：1978-03-27
IPC分类号： H01L27/04 , H01L21/306 , H01L21/321 , H01L21/3215 , H01L21/331 , H01L21/768 , H01L21/822 , H01L21/8244 , H01L23/522 , H01L27/11 , H01L29/73 , H01L29/78 , B01J17/00
CPC分类号： H01L21/321 , H01L21/32155 , H01L21/76885 , Y10S257/904
摘要： A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.
摘要翻译： 公开了在制造MOS集成电路期间用多晶硅多晶硅电阻器形成多晶硅层之间的电接触区域的工艺。 不需要临界对准的接触区域可以直接形成在有源沟道或掩埋（衬底）接触件上。 在第一多晶硅层上的接触区域的位置处形成氮化硅掩模，从而允许在衬底的其余部分上生长厚的氧化物。 在去除氮化硅掩模之后，形成第二多晶硅层，其在接触区域与第一层接触并限定电阻器。 掺杂步骤用于建立电阻的电阻。 该过程允许例如使用面积约为1.5密耳2的多晶硅负载的静态（双稳态）MOS存储单元的制造。
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公开(公告)号：US4026733A
公开(公告)日：1977-05-31
申请号：US626857
申请日：1975-10-29
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/3215 , H01L21/336 , H01L21/26
CPC分类号： H01L29/66575 , H01L21/28 , H01L21/32132 , H01L21/32155 , Y10S148/122 , Y10S438/947
摘要： A process and method for accurately defining polycrystalline silicon patterns from a masking member. The critical dimensions of the silicon patterns are controlled by a diffusion step. Self-limiting etching is achieved through use of an etchant which discriminates between doped and undoped polycrystalline silicon. The process which provides significant advantages in production processing, permits fabrication of narrower gates and smoother edges on elongated silicon strips.
摘要翻译： 一种用于从遮蔽构件精确地限定多晶硅图案的方法和方法。 通过扩散步骤控制硅图案的关键尺寸。 通过使用鉴别掺杂和未掺杂多晶硅的蚀刻剂来实现自限蚀刻。 在生产加工中提供显着优点的方法允许在细长的硅带上制造较窄的浇口和更平滑的边缘。
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公开(公告)号：US4026740A
公开(公告)日：1977-05-31
申请号：US626855
申请日：1975-10-29
申请人： William H. Owen, III
发明人： William H. Owen, III
IPC分类号： H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/3215 , H01L21/312
CPC分类号： H01L21/033 , H01L21/28 , H01L21/32132 , H01L21/32155 , Y10S148/051 , Y10S148/106 , Y10S148/111 , Y10S148/122 , Y10S438/924 , Y10S438/947
摘要： A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.
摘要翻译： 一种用于从多晶硅层制造窄硅元件的工艺，例如用于MOS场效应晶体管的栅极。 掩模的边缘用于限定在下层硅层上露出窄线的间隙。 通过间隙在硅层中形成掺杂区域，然后选择性地蚀刻该层。 制造的硅元件的关键尺寸由掺杂剂的扩散程度确定，并且基本上与掩模公差无关。
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公开(公告)号：US5084667A
公开(公告)日：1992-01-28
申请号：US462311
申请日：1989-12-22
CPC分类号： G11C17/14 , G05B19/075 , H03H7/25 , G05B2219/23029 , G05B2219/23041
摘要： A variable impedance circuit for use in an external circuit is disclosed. The impedance value is selected by an external circuit. The variable impedance is generated between two terminals which are accessible for connection to external circuitry. The impedance provided between these terminals is determined by a control circuit responsive to electrical signals coupled to the control circuit. An internal register in the control circuit stores a value which specifies the impedance between the two terminals. The stored value is copied into a programmable nonvolatile read-only memory in response to a first predetermined electrical signal. Similarly, the value stored in the read-only memory is selectively copied into the internal control circuit register in response to a second predetermined electrical signal. A number of embodiments of variable impedance elements are disclosed which minimize the number of separate resistors required to achieve the equivalent resolution achievable using a series arrangement of resistors.
摘要翻译： 公开了一种用于外部电路的可变阻抗电路。 阻抗值由外部电路选择。 在可连接外部电路的两个端子之间产生可变阻抗。 这些端子之间提供的阻抗由响应耦合到控制电路的电信号的控制电路决定。 控制电路中的内部寄存器存储指定两个端子之间的阻抗的值。 响应于第一预定电信号将存储的值复制到可编程非易失性只读存储器中。 类似地，响应于第二预定电信号，将存储在只读存储器中的值选择性地复制到内部控制电路寄存器中。 公开了可变阻抗元件的多个实施例，其最小化实现使用电阻器的串联布置可实现的等效分辨率所需的单独电阻器的数量。
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公开(公告)号：US4450402A
公开(公告)日：1984-05-22
申请号：US252232
申请日：1981-04-08
申请人： William H. Owen, III
发明人： William H. Owen, III
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31701
摘要： An integrated testing apparatus provides bidirectional coupling of a high voltage either from an internal source on an integrated circuit to a first external pin on the integrated circuit package, or to the output point of said internal source of high voltage from a voltage source external to the integrated circuit package that is coupled to said first external pin, said coupling occurring in response to an enabling signal externally impressed on a second external pin on said integrated circuit package. The testing apparatus is substantially transparent to normal integrated circuit operation when said enabling signal is removed from said second external pin.
摘要翻译： 集成测试装置提供从集成电路上的内部源到集成电路封装上的第一外部引脚的高电压双向耦合，或者提供所述内部高电压源的输出点， 集成电路封装，其耦合到所述第一外部引脚，所述耦合响应于外部施加在所述集成电路封装上的第二外部引脚上的使能信号而发生。 当所述使能信号从所述第二外部引脚移除时，所述测试装置对正常集成电路操作基本上是透明的。
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公开(公告)号：US4404475A
公开(公告)日：1983-09-13
申请号：US252231
申请日：1981-04-08
摘要： An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.
摘要翻译： 一种用于产生调节的高电压隧道脉冲的集成电路系统，其电压电平随着电子穿过相应的第一和第二区域之间的一个或多个电介质间隙而引起的电压所需的电压电平变化。 将初始电子隧穿的电压电平与预定的电压余量进行比较，以使所述产生的隧穿电压脉冲的电压电平等于所检测的隧穿电压和所述电压余量之和。 然后在隧道脉冲放电之前，将隧道电压脉冲基本保持在该电平预定的持续时间。
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