公开(公告)号：US20090140426A1

公开(公告)日：2009-06-04

申请号：US11965365

申请日：2007-12-27

申请人： Woong Sun LEE ,  Il Hwan CHO ,  Myung Geun PARK ,  Cheol Ho JOH ,  Eun Hye DO ,  Ki Young KIM ,  Ji Eun KIM ,  Jong Hyun NAM

发明人： Woong Sun LEE ,  Il Hwan CHO ,  Myung Geun PARK ,  Cheol Ho JOH ,  Eun Hye DO ,  Ki Young KIM ,  Ji Eun KIM ,  Jong Hyun NAM

IPC分类号： H01L23/48 ,  H01L21/02

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81395 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H05K3/282 ,  H05K2201/10674 ,  H05K2203/0568 ,  H05K2203/1361 ,  H05K2203/1554 ,  H01L2924/00 ,  H01L2224/05599

摘要： A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.

摘要翻译： 倒装芯片封装包括衬底和半导体芯片。 基板包括基板主体，具有端子部分的金属布线，其中一部分设置在基板主体中，形成在基板主体上的阻焊图案具有用于暴露端子部分的开口，以及有机抗氧化层， 覆盖终端部分。 半导体芯片具有穿过（例如，穿透）有机抗氧化层并且电连接到端子部分的凸块。 本发明防止了端子部分的氧化，并且容易地将半导体芯片的凸起与基板的端子部分耦合，因为包括有机物的抗氧化层在包括铜的端子部分的表面上形成 容易氧化。

公开(公告)号：US20110272820A1

公开(公告)日：2011-11-10

申请号：US13096143

申请日：2011-04-28

申请人： Kyu Won LEE ,  Cheol Ho JOH ,  Eun-Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

发明人： Kyu Won LEE ,  Cheol Ho JOH ,  Eun-Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

IPC分类号： H01L23/48 ,  H01L21/82

CPC分类号： H01L23/481 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

摘要翻译： 堆叠半导体封装包括半导体封装模块，其包括多个半导体封装，每个半导体封装具有第一表面，背离第一表面的第二表面，连接第一表面和第二表面的侧表面和形成在第一表面上的通孔 侧表面通过第一表面和第二表面并且堆叠成使得它们的通孔彼此垂直连接;以及粘合构件，其形成在半导体封装之间并将半导体封装彼此附接，主基板 支撑半导体封装模块，并在其面向半导体封装模块的第三表面上形成与通孔对准的主连接焊盘，以及形成在通孔中的导电连接构件，并将半导体封装与 主连接垫

公开(公告)号：US20100092718A1

公开(公告)日：2010-04-15

申请号：US12346097

申请日：2008-12-30

申请人： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

发明人： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC分类号： B32B3/02 ,  B32B37/00

CPC分类号： H01L21/6835 ,  C09J7/20 ,  C09J2201/28 ,  C09J2203/326 ,  H01L21/67005 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10T156/10 ,  Y10T156/17 ,  Y10T428/215

摘要： A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive member is disposed at the first region. The second adhesive member is disposed at the third region.

摘要翻译： 提出了一种晶片安装带，晶片处理设备和使用晶片安装带用于晶片间隔操作的相关方法。 晶片安装带包括带体，第一粘合构件和第二粘合构件。 带体具有第一区域，第二区域和第三区域。 带体的第一区域用于设置在晶片上。 带体的第二区域沿着第一区域的周边限定。 带体的第三区域沿着第二区域的周边限定。 第一粘合构件设置在第一区域。 第二粘合构件设置在第三区域。

公开(公告)号：US20110272798A1

公开(公告)日：2011-11-10

申请号：US13038831

申请日：2011-03-02

申请人： Kyu Won LEE ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

发明人： Kyu Won LEE ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Hee Min SHIN

IPC分类号： H01L23/28

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.

摘要翻译： 芯片单元包括：第一半导体芯片和第二半导体芯片，其布置成使得其用于形成第一焊盘和第二焊盘的表面彼此面对; 第一和第二连接构件，设置在第一和第二半导体芯片的表面上，用于形成第一和第二接合焊盘，并且具有一端与第一和第二接合焊盘连接的再分配线，另一端突出超过 第一和第二半导体芯片和薄膜; 插入在所述第一连接构件和所述第二连接构件之间的粘合构件; 并且通过图案通过粘合构件并将第一和第二连接构件的再分配线的突出部彼此连接。

公开(公告)号：US20110189928A1

公开(公告)日：2011-08-04

申请号：US13050325

申请日：2011-03-17

申请人： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

发明人： Hee Min SHIN ,  Cheol Ho JOH ,  Eun Hye DO ,  Ji Eun KIM ,  Kyu Won LEE

IPC分类号： B24B1/00 ,  B32B3/14 ,  C09J7/02

CPC分类号： H01L21/6835 ,  C09J7/20 ,  C09J2201/28 ,  C09J2203/326 ,  H01L21/67005 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10T156/10 ,  Y10T156/17 ,  Y10T428/215

摘要： A wafer mount tape, a wafer processing apparatus and an associated method of using the wafer mount tape for use in wafer thinning operations is presented. The wafer mount tape includes a tape body, a first adhesive member and a second adhesive member. The tape body has a first region, a second region and a third region. The first region of the tape body is for being disposed onto a wafer. The second region of the tape body is defined along a periphery of the first region. The third region of the tape body is defined along a periphery of the second region. The first adhesive is member is disposed at the first region. The second adhesive member is disposed at the third region.

摘要翻译： 提出了一种晶片安装带，晶片处理设备和使用晶片安装带用于晶片间隔操作的相关方法。 晶片安装带包括带体，第一粘合构件和第二粘合构件。 带体具有第一区域，第二区域和第三区域。 带体的第一区域用于设置在晶片上。 带体的第二区域沿着第一区域的周边限定。 带体的第三区域沿着第二区域的周边限定。 第一粘合剂是构件设置在第一区域。 第二粘合构件设置在第三区域。

公开(公告)号：US20090096075A1

公开(公告)日：2009-04-16

申请号：US11940522

申请日：2007-11-15

申请人： Cheol Ho JOH

发明人： Cheol Ho JOH

IPC分类号： H01L23/50 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads.

摘要翻译： 堆叠的半导体封装包括具有第一和第二接触焊盘的衬底。 第一堆叠封装组被布置在基板上，并且第一堆叠封装组包括以阶梯形式堆叠以暴露第一边缘焊盘的第一半导体芯片。 第一导电线用于电耦合第一边缘接合焊盘和第一接触焊盘。 粘合构件设置在最上面的第一半导体芯片上，并且第二堆叠封装组设置在粘合构件上。 第二堆叠封装组包括以阶梯形式堆叠以暴露第二边缘焊盘的第二半导体芯片。 当第二堆叠封装组设置在粘合构件上时，最下面的第二半导体芯片与最上面的第一半导体芯片对准。 第二导线用于电耦合第二边缘焊盘和第二接触焊盘。

公开(公告)号：US20080061406A1

公开(公告)日：2008-03-13

申请号：US11760239

申请日：2007-06-08

申请人： Cheol Ho JOH

发明人： Cheol Ho JOH

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a semiconductor chip; and an encapsulant for covering the semiconductor chip, such that the encapsulant includes a molding part for covering the semiconductor chip to protect the semiconductor chip from the external environment; and an electromagnetic shielding part for covering an outer surface of the molding part and containing therein electrically conductive particles for shielding an electromagnetic wave radiated from the semiconductor chip to the outside and an electromagnetic wave incident from the outside to the semiconductor chip.

摘要翻译： 半导体封装包括半导体芯片; 以及用于覆盖所述半导体芯片的密封剂，使得所述密封剂包括用于覆盖所述半导体芯片以将所述半导体芯片与外部环境保护的模制部件; 以及电磁屏蔽部件，用于覆盖模制部件的外表面并且包含用于屏蔽从半导体芯片辐射到外部的电磁波的导电颗粒和从外部入射到半导体芯片的电磁波。