公开(公告)号：US20140073089A1

公开(公告)日：2014-03-13

申请号：US14077877

申请日：2013-11-12

Applicant: XINTEC INC.

Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG

IPC: H01L25/00

CPC classification number: H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US20130256869A1

公开(公告)日：2013-10-03

申请号：US13900494

申请日：2013-05-22

Applicant: XINTEC INC.

Inventor： Baw-Ching PERNG ,  Chun-Lung HUANG

IPC: H01L23/433 ,  H01L21/56

CPC classification number: H01L23/433 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00

Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

Abstract translation: 一个实施例提供了一种芯片封装，其包括基板，从基板的上表面向下延伸的空腔，覆盖基板并保形地覆盖空腔的侧壁和底部的金属层，具有上表面并位于 所述空腔中的所述金属层，其中所述上表面不低于所述空腔外部的所述金属层的上表面，并且所述保护层覆盖所述芯片。

公开(公告)号：US20130193520A1

公开(公告)日：2013-08-01

申请号：US13828537

申请日：2013-03-14

Applicant: Xintec Inc.

Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG ,  Ching-Yu NI ,  Yun-Jui HSIEH ,  Wei-Ming CHEN ,  Chia-Lun TSAI ,  Chia-Ming CHENG

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。