公开(公告)号：US08030161B2

公开(公告)日：2011-10-04

申请号：US12121591

申请日：2008-05-15

申请人： Xiangfeng Duan ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

发明人： Xiangfeng Duan ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

摘要翻译： 非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。 隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。 栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。 根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。 优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。 根据另一实施例，非易失性存储单元的栅极包括第一子层和第一子层上具有不同宽度的第二子层。

公开(公告)号：US20080290394A1

公开(公告)日：2008-11-27

申请号：US12121591

申请日：2008-05-15

申请人： Xiangfeng DUAN ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

发明人： Xiangfeng DUAN ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

IPC分类号： H01L29/00 ,  H01L21/3205

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

摘要翻译： 非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。 隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。 栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。 根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。 优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。 根据另一实施例，非易失性存储单元的栅电极包括第一子层和第一子层上具有不同宽度的第二子层。

公开(公告)号：US07871870B2

公开(公告)日：2011-01-18

申请号：US12703043

申请日：2010-02-09

申请人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

发明人： Shahriar Mostarshed ,  Jian Chen ,  Francisco A. Leon ,  Yaoling Pan ,  Linda T. Romano

IPC分类号： H01L21/00 ,  H01L27/108

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

摘要翻译： 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

公开(公告)号：US07760980B2

公开(公告)日：2010-07-20

申请号：US11514291

申请日：2006-08-31

申请人： Lawrence C. West ,  Gregory L. Wojcik ,  Francisco A. Leon ,  Yonah Cho ,  Andreas Goebel

发明人： Lawrence C. West ,  Gregory L. Wojcik ,  Francisco A. Leon ,  Yonah Cho ,  Andreas Goebel

IPC分类号： G02B6/10 ,  G02B6/13

CPC分类号： G02B6/132 ,  G02B6/12004 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12123 ,  G02B2006/12176 ,  H01L31/02327 ,  H01L31/1812 ,  Y02E10/50

摘要： A method of fabricating on a substrate an optical detector in an optical waveguide, the method involving: forming at least one layer on a surface of the substrate, said at least one layer comprising SiGe; implanting an impurity into the at least one layer over a first area to form a detector region for the optical detector; etching into the at least one layer in a first region and a second region to form a ridge between the first and second regions, said ridge defining the optical detector and the optical waveguide; filling the first and second regions with a dielectric material having a lower refractive index than SiGe; and after filling the first and second regions with the dielectric material, removing surface material to form a planarized upper surface.

摘要翻译： 一种在光波导中在基板上制造光检测器的方法，所述方法包括：在所述基板的表面上形成至少一层，所述至少一层包括SiGe; 在第一区域上将杂质注入到所述至少一个层中以形成用于所述光学检测器的检测器区域; 在第一区域和第二区域中蚀刻到所述至少一个层中以在所述第一和第二区域之间形成脊，所述脊限定所述光学检测器和所述光波导; 用具有比SiGe低的折射率的电介质材料填充第一和第二区域; 并且在用电介质材料填充第一和第二区域之后，去除表面材料以形成平坦化的上表面。

公开(公告)号：US6103429A

公开(公告)日：2000-08-15

申请号：US161844

申请日：1998-09-28

申请人： Brian S. Doyle ,  Francisco A. Leon ,  Richard Elliot Schenker

发明人： Brian S. Doyle ,  Francisco A. Leon ,  Richard Elliot Schenker

IPC分类号： G03F1/00 ,  G03F1/28 ,  G03F1/30 ,  G03F9/00

CPC分类号： G03F1/28 ,  G03F1/30

摘要： A technique for fabricating a phase shift mask with multiple phase shifts by using self-aligned spacers to form phase shifting regions on a surface of a mask substrate. Three phase shifting regions are formed corresponding to 180.degree./120.degree./60.degree. phase shifts or delays on the surface of mask substrate. The three phase shifting regions are fabricated from three different dielectric materials, each having a different refractive indices. The first phase shifting region is formed by a photolithography technique, but the other two phase shifting regions are formed by the formation of self-aligned spacers. In an alternative technique, all three of the phase shifting regions are formed by the use of self-aligned spacers.

摘要翻译： 一种通过使用自对准隔板来制造具有多个相移的相移掩模以在掩模基板的表面上形成相移区域的技术。 形成对应于掩模基板表面上的180°/ 120°/ 60°相移或延迟的三个相移区域。 三个相移区域由三种不同的介电材料制成，各自具有不同的折射率。 通过光刻技术形成第一相移区域，但是通过形成自对准间隔物形成其它两个相移区域。 在替代技术中，通过使用自对准间隔物形成所有三个相移区域。

公开(公告)号：US5586230A

公开(公告)日：1996-12-17

申请号：US148181

申请日：1993-11-05

申请人： Francisco A. Leon ,  Satoshi Tazawa

发明人： Francisco A. Leon ,  Satoshi Tazawa

IPC分类号： G06F17/50 ,  G06T17/10 ,  G06T17/00

CPC分类号： G06T17/10

摘要： A method for deforming a solid and avoiding the creation of self-intersecting solid structures in a topography simulator. In a topography simulated based on a solids modeling system, self-intersecting structures are solids which have boundaries that intersect. Such self-intersecting structures are invalid and cannot be processed. A general method for sweeping a solid surface to create a deformed solid and avoid the creation of self-intersecting solid structures is described, which include the steps of: providing a material solid with a surface represented as one or more segments; constructing a first segment solid for a first segment; performing a boolean set operation between the solid being swept and the first segment solid creating a temporary first solid; identifying a second segment; constructing a second segment solid for the second segment; and performing the boolean set operation between said temporary first solid and said first segment solid creating said deformed first solid. The case where simultaneous deposition and etch is occurring requires utilizes separate temporary deposition and etch solids for each segment both of which are swept to create the deformed solid.

摘要翻译： 一种使固体变形并避免在地形模拟器中产生自相交固体结构的方法。 在基于实体建模系统模拟的地形中，自相交结构是具有相交边界的固体。 这种自相交结构无效，无法处理。 描述了用于扫掠固体表面以产生变形固体并避免产生自相交固体结构的一般方法，其包括以下步骤：提供具有表示为一个或多个段的表面的材料固体; 为第一段构造第一段固体; 在被扫描的实体和创建临时的第一实体的第一段固定之间执行布尔组操作; 识别第二段; 为第二段构造第二段实体; 以及在所述临时第一实体和所述第一段固体之间执行布尔组合操作，创建所述变形的第一固体。 同时沉积和蚀刻发生的情况需要对每个段进行单独的临时沉积和蚀刻固体，两个扫描都被扫过以产生变形的固体。

公开(公告)号：US20090269878A1

公开(公告)日：2009-10-29

申请号：US12420558

申请日：2009-04-08

申请人： Francisco A. Leon ,  Lawrence C. West ,  Yuichi Wada ,  Gregory L. Wojcik ,  Stephen Moffatt

发明人： Francisco A. Leon ,  Lawrence C. West ,  Yuichi Wada ,  Gregory L. Wojcik ,  Stephen Moffatt

IPC分类号： H01L21/20

CPC分类号： G02B6/12004 ,  G02B2006/12061 ,  H01L31/0232 ,  H01L31/0288 ,  H01L31/105 ,  H01L31/1812 ,  Y02E10/50

摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

摘要翻译： 一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

公开(公告)号：US06730988B2

公开(公告)日：2004-05-04

申请号：US10338435

申请日：2003-01-08

申请人： Francisco A. Leon ,  Everett X. Wang

发明人： Francisco A. Leon ,  Everett X. Wang

IPC分类号： H01L2906

CPC分类号： G02B6/136 ,  G02B6/125 ,  G02B2006/1213

摘要： Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.

公开(公告)号：US5367465A

公开(公告)日：1994-11-22

申请号：US904005

申请日：1992-06-24

申请人： Satoshi Tazawa ,  Kazuyuki Saito ,  Francisco A. Leon

发明人： Satoshi Tazawa ,  Kazuyuki Saito ,  Francisco A. Leon

IPC分类号： H01L21/302 ,  G06F17/50 ,  G06T17/20 ,  H01L21/3065 ,  G06F15/72

CPC分类号： G06T17/20

摘要： A method for creating regular triangular grid representations of a solid surface from a representation comprised of a plurality of polygons. Such a regular grid is necessary in order to accurately deform a solid during simulation of a process step. The method of the preferred embodiment is comprised generally of the steps of: removing any holes defined by the polygon face; placing a new edge between a first and second vertex of the polygon face; discarding the new edge if the new edge lies outside the polygon face or if the new edge intersects an existing edge of the polygon face; adding the new edge to the polygon face if the new edge does not lie outside the polygon face; identifying a triangle being created by the new edge and existing edges of the polygon; forming a new polygon face from the edges creating a triangle; and repeating the above steps until all polygon faces are triangulated. Once the triangulation of the polygons is completed, adjustments to the triangles is made in order to have only triangles of uniform size.

摘要翻译： 一种从由多个多边形构成的表示形成固体表面的规则三角形网格表示的方法。 为了在模拟过程步骤期间准确地变形固体，需要这样的规则网格。 优选实施例的方法通常包括以下步骤：去除由多边形面限定的任何孔; 在多边形面的第一和第二顶点之间放置新的边缘; 如果新边缘位于多边形面之外或如果新边缘与多边形面的现有边缘相交，则丢弃新边缘; 如果新边缘不在多边形面之外，则将新边添加到多边形面; 识别由新边缘和多边形的现有边缘创建的三角形; 从边缘形成新的多边形面，创建三角形; 并重复上述步骤直到所有多边形面被三角测量。 一旦完成了多边形的三角测量，就可以对三角形进行调整，以便仅具有均匀尺寸的三角形。

公开(公告)号：US06898781B2

公开(公告)日：2005-05-24

申请号：US10631625

申请日：2003-07-30

申请人： Vivek K. Singh ,  John Ernst Bjorkholm ,  Francisco A. Leon

发明人： Vivek K. Singh ,  John Ernst Bjorkholm ,  Francisco A. Leon

IPC分类号： G03F1/24 ,  G03F1/36 ,  G03F7/20 ,  G06F17/10 ,  G06F17/50 ,  G06F19/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70941

摘要： A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.

摘要翻译： 一种方法，包括基于衬底布局上的投影结构的特征密度确定第一耀斑卷积，基于用于给定衬底布局的掩模确定第二耀斑卷积，通过将第一耀斑卷积和第二扩张卷积相加来确定系统闪光变化 闪耀卷积，并且基于系统耀斑变化确定临界尺寸变化。