公开(公告)号：US20120097436A1

公开(公告)日：2012-04-26

申请号：US12973604

申请日：2010-12-20

申请人： YING-TSO LAI ,  YU-CHANG PAI

发明人： YING-TSO LAI ,  YU-CHANG PAI

IPC分类号： H05K1/09

CPC分类号： H05K1/116 ,  H05K3/3447

摘要： A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole extends through the printed circuit board. A thermal engraving is defined in the surface of the layer, surrounding the through hole and without being covered by the layer of copper. The thermal engraving includes a first opening and a second opening. The first opening of the thermal engraving faces an output terminal of the power supply, and is non-contiguous with the second opening.

摘要翻译： 印刷电路板包括一层。 铜层被覆盖在该层的表面上。 通孔延伸穿过印刷电路板。 在该表面中限定了热雕刻，围绕通孔并且不被铜层覆盖。 热雕刻包括第一开口和第二开口。 热雕刻的第一开口面向电源的输出端，并且与第二开口不连续。

公开(公告)号：US20120018199A1

公开(公告)日：2012-01-26

申请号：US12870999

申请日：2010-08-30

申请人： YING-TSO LAI ,  YU-CHANG PAI

发明人： YING-TSO LAI ,  YU-CHANG PAI

IPC分类号： H05K1/09

CPC分类号： H05K3/3447 ,  H05K1/0271 ,  H05K2201/093 ,  H05K2201/0969

摘要： A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole passes through the printed circuit board. An approximately C-shaped thermal engraving is defined in the surface of the layers, surrounding the through hole and without being covered by the layer of copper. An opening of the thermal engraving faces an output terminal of the power supply.

摘要翻译： 印刷电路板包括一层。 铜层被覆盖在该层的表面上。 通孔穿过印刷电路板。 在层的表面中限定大致C形的热雕刻，围绕通孔并且不被铜层覆盖。 热雕刻的开口面向电源的输出端子。

公开(公告)号：US20090294168A1

公开(公告)日：2009-12-03

申请号：US12272797

申请日：2008-11-18

申请人： YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU ,  YING-TSO LAI

发明人： YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU ,  YING-TSO LAI

IPC分类号： H05K1/11

CPC分类号： H05K1/116 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09636

摘要： A printed circuit board includes a first layout layer, a second layout layer, a copper foil layer, a first via and a second via. The first layout layer has a first signal line and a second signal line, each of which has a curved first portion. The second layout layer has a third signal line and a fourth signal line, each of which also has a curved first portion. The curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line are coupled to the first via and the second via. In this case, the curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line cooperatively generate spiral inductance characteristic.

摘要翻译： 印刷电路板包括第一布局层，第二布局层，铜箔层，第一通孔和第二通孔。 第一布局层具有第一信号线和第二信号线，每条信号线都具有弯曲的第一部分。 第二布局层具有第三信号线和第四信号线，每条信号线还具有弯曲的第一部分。 第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分耦合到第一通孔和第二通孔。 在这种情况下，第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分协同地产生螺旋电感特性。

公开(公告)号：US20110094787A1

公开(公告)日：2011-04-28

申请号：US12647431

申请日：2009-12-25

申请人： YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

发明人： YING-TSO LAI ,  CHUN-JEN CHEN ,  YU-CHANG PAI ,  PEI-CHUN LIN ,  CHIN-HUI CHEN ,  HSIAO-PING HUANG

IPC分类号： H05K1/11 ,  H05K3/10

CPC分类号： H05K1/116 ,  H05K1/0201 ,  H05K3/3447 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2203/0242 ,  Y10T29/49155

摘要： A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole passes through the printed circuit board. A number of thermal engravings are defined in the layer around the through hole. Each thermal engraving is a groove defined in the surface of the layer, without covered with the layer of copper. The number of thermal engravings are not in contact with each other.

摘要翻译： 印刷电路板包括一层。 铜层被覆盖在该层的表面上。 通孔穿过印刷电路板。 在通孔周围的层中限定了许多热雕刻。 每个热雕刻是在层的表面中限定的凹槽，而不被铜层覆盖。 热雕刻的数量彼此不接触。

公开(公告)号：US20090166058A1

公开(公告)日：2009-07-02

申请号：US12042348

申请日：2008-03-05

申请人： YING-TSO LAI ,  YU-CHANG PAI ,  SHOU-KUO HSU

发明人： YING-TSO LAI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/00

CPC分类号： H05K1/0216 ,  H05K2201/09027 ,  H05K2201/093

摘要： A printed circuit board (PCB) includes a power layer having a base portion, and at least two extending portions. The at least two extending portions are extended from edges near at least one corner of the base portion for preventing the PCB from forming constructive interferences and lowering the resonance magnitude thereof.

摘要翻译： 印刷电路板（PCB）包括具有基部的功率层和至少两个延伸部分。 至少两个延伸部分从靠近基部的至少一个拐角处的边缘延伸，以防止PCB形成结构性干扰并降低其共振幅度。

公开(公告)号：US20110253424A1

公开(公告)日：2011-10-20

申请号：US12780960

申请日：2010-05-17

申请人： YING-TSO LAI ,  HSIAO-YUN SU

发明人： YING-TSO LAI ,  HSIAO-YUN SU

IPC分类号： H05K1/00

CPC分类号： H05K1/0253 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/028 ,  H05K2201/09236 ,  H05K2201/0969

摘要： A FPCB includes a signal layer, a ground layer, and a dielectric layer lying between the signal layer and the ground layer. At least one high speed signal transmission line is formed on the signal layer. The ground layer has a copper-removed area corresponding to the transmission line. Two ground lines are symmetrically disposed at two opposite sides of the signal transmission line and substantially parallel to the signal transmission line, each ground line and the signal transmission line is spaced at a first predetermined distance. Each ground line and the signal transmission line are spaced at a first predetermined distance.

摘要翻译： FPCB包括位于信号层和接地层之间的信号层，接地层和电介质层。 在信号层上形成至少一条高速信号传输线。 接地层具有对应于传输线的铜去除区域。 两个接地线对称地设置在信号传输线的两个相对侧并且基本上平行于信号传输线，每个接地线和信号传输线以第一预定距离间隔开。 每个接地线和信号传输线以第一预定距离隔开。

公开(公告)号：US20100253383A1

公开(公告)日：2010-10-07

申请号：US12425394

申请日：2009-04-17

申请人： HSIAO-YUN SU ,  YING-TSO LAI ,  SHOU-KUO HSU

发明人： HSIAO-YUN SU ,  YING-TSO LAI ,  SHOU-KUO HSU

IPC分类号： H03K19/003

CPC分类号： H05K1/0246 ,  H05K2201/044 ,  H05K2201/09727

摘要： A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines.

摘要翻译： 用于多个负载的电路拓扑包括用于发送驱动信号的驱动端子，多个发送线路和可操作以从驱动端子接收驱动信号的多个负载。 负载数量通过传输线数量逐个连接到驱动端子。 距离驱动终端最近和最远的发送线数目的两条发送线都大于其他发送线的宽度。

公开(公告)号：US20130168145A1

公开(公告)日：2013-07-04

申请号：US13626896

申请日：2012-09-26

申请人： YING-TSO LAI ,  HSIAO-YUN SU

发明人： YING-TSO LAI ,  HSIAO-YUN SU

IPC分类号： H01G4/005 ,  H05K1/16

CPC分类号： H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01G4/38 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09672

摘要： A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

摘要翻译： 电容器包括彼此相对的至少两个电极层和位于所述至少两个电极层之间的电介质层。 至少两个电极层具有相反的极性。 每个电极层包括正极和负极。 正电极包括大致均匀间隔开并且平行布置的多个第一耦合部分。 负极包括大致均匀间隔开并且平行布置的多个第二联接部。 每个电极层的正电极和负电极是共面的，并且多个第一耦合部分与多个第二耦合部分交织。

公开(公告)号：US20130163646A1

公开(公告)日：2013-06-27

申请号：US13548223

申请日：2012-07-13

申请人： YING-TSO LAI ,  HSIAO-YUN SU ,  DAN-CHEN WU ,  SHIN-TING YEN

发明人： YING-TSO LAI ,  HSIAO-YUN SU ,  DAN-CHEN WU ,  SHIN-TING YEN

IPC分类号： H04L27/01

CPC分类号： H04L25/03878

摘要： A method for setting a signal-equalizing system for use in an electronic device includes the following steps. Outputting a connection status of each channel and a number of misconnect options respectively associated with each channel to a display unit of the electronic device. Then, detecting whether at least one misconnect option is selected. If yes, determining a misconnected channel and adjusting the receiving setting for the receiving port of the misconnected channel to match with the transmitting setting for the transmitting port of the misconnected channel according to settings for each channel stored in the electronic device. The stored settings for each channel include a transmitting setting for the transmitting port of the channel and a receiving setting for the receiving port of the channel that matches the transmitting setting.

摘要翻译： 一种用于设置用于电子设备的信号均衡系统的方法包括以下步骤。 将每个通道的连接状态和与每个通道分别相关联的多个错误连接选项输出到电子设备的显示单元。 然后，检测是否选择了至少一个错误连接选项。 如果是，则根据存储在电子设备中的每个通道的设置，确定错误连接的信道并且调整误连接信道的接收端口的接收设置以与错连接信道的发送端口的发送设置相匹配。 每个通道的存储设置包括通道发送端口的发送设置和与发送设置匹配的通道接收端口的接收设置。

公开(公告)号：US20120229993A1

公开(公告)日：2012-09-13

申请号：US13108997

申请日：2011-05-17

申请人： WEI-CHIEH CHOU ,  YING-TSO LAI ,  YUNG-CHIEH CHEN

发明人： WEI-CHIEH CHOU ,  YING-TSO LAI ,  YUNG-CHIEH CHEN

IPC分类号： H05K7/14 ,  H05K1/02 ,  H05F3/00

CPC分类号： H05K9/0067 ,  H05K1/0215 ,  H05K1/0259 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10189

摘要： An exemplary antistatic circuit board includes a first outer layer, a second outer layer, a first ground layer, and a second ground layer. The first ground layer and the second ground layer are positioned between the first outer layer and the second outer layer. The first ground layer is adjacent to the first outer layer and the second ground layer is adjacent to the second outer layer. The antistatic circuit board defines two position holes each penetrating through the first ground layer and the second ground layer. Two circuit grounds are wired on the first ground layer and the second ground layer, respectively. The second ground layer further includes a chassis ground. Each of the position holes also penetrates through the chassis ground.

摘要翻译： 示例性的抗静电电路板包括第一外层，第二外层，第一接地层和第二接地层。 第一接地层和第二接地层位于第一外层和第二外层之间。 第一接地层与第一外层相邻，第二接地层与第二外层相邻。 抗静电电路板限定了穿过第一接地层和第二接地层的两个位置孔。 两个电路接地分别布置在第一接地层和第二接地层上。 第二接地层还包括底盘接地。 每个位置孔也穿过底盘地面。