公开(公告)号：US20140183730A1

公开(公告)日：2014-07-03

申请号：US14199078

申请日：2014-03-06

申请人： Nae HISANO ,  Shigeo OHASHI ,  Yasuo OSONE ,  Yasuhiro NAKA ,  Hiroyuki TENMEI ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO ,  Hideharu MIYAKE ,  Shiro UCHIYAMA

发明人： Nae HISANO ,  Shigeo OHASHI ,  Yasuo OSONE ,  Yasuhiro NAKA ,  Hiroyuki TENMEI ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO ,  Hideharu MIYAKE ,  Shiro UCHIYAMA

IPC分类号： H01L23/00 ,  H01L23/34

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/473 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

摘要翻译： 半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体 液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

公开(公告)号：US20080136024A1

公开(公告)日：2008-06-12

申请号：US11947393

申请日：2007-11-29

申请人： Yasuhiro NAKA ,  Hiroyuki Tenmei ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO

发明人： Yasuhiro NAKA ,  Hiroyuki Tenmei ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device provided by preventing connection failure caused by misalignment of a semiconductor element having fine and narrow-pitched bumps, a guide for preventing the misalignment is formed by an insulating resin layer around a connection electrode. The insulating resin layer has a thickness defined in relation to an angle θ formed by a side wall of the opening and alignment accuracy δ for the bump. Specifically, the thickness of the insulating resin layer may be δ tan θ or more.

摘要翻译： 在通过防止由具有细小和窄凸起的半导体元件的未对准引起的连接故障而提供的半导体器件中，通过连接电极周围的绝缘树脂层形成用于防止未对准的引导件。 绝缘树脂层具有相对于由开口的侧壁形成的角度θ和用于凸起的对准精度δ而定义的厚度。 具体地说，绝缘树脂层的厚度可以是δtanθ以上。

公开(公告)号：US20100171213A1

公开(公告)日：2010-07-08

申请号：US12683085

申请日：2010-01-06

申请人： Nae HISANO ,  Shigeo OHASHI ,  Yasuo OSONE ,  Yasuhiro NAKA ,  Hiroyuki TENMEI ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO ,  Hideharu MIYAKE ,  Shiro UCHIYAMA

发明人： Nae HISANO ,  Shigeo OHASHI ,  Yasuo OSONE ,  Yasuhiro NAKA ,  Hiroyuki TENMEI ,  Kunihiko NISHI ,  Hiroaki IKEDA ,  Masakazu ISHINO ,  Hideharu MIYAKE ,  Shiro UCHIYAMA

IPC分类号： H01L23/473 ,  H01L23/488 ,  F28F7/00

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/473 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

摘要翻译： 半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体 液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

公开(公告)号：US20090072414A1

公开(公告)日：2009-03-19

申请号：US12187622

申请日：2008-08-07

申请人： Hiroyuki TENMEI ,  Kunihiko NISHI ,  Yasuhiro NAKA ,  Nae HISANO ,  Hiroaki IKEDA ,  Masakazu ISHINO

发明人： Hiroyuki TENMEI ,  Kunihiko NISHI ,  Yasuhiro NAKA ,  Nae HISANO ,  Hiroaki IKEDA ,  Masakazu ISHINO

IPC分类号： H01L23/52 ,  H01L21/30

CPC分类号： H01L24/73 ,  H01L21/76898 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/83907 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27

摘要： A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

摘要翻译： 提供半导体衬底的接合方法（三维安装），以通过施加的粘合剂顺序地接合形成有耦合凸块的硅晶片的主表面和形成有焊盘的另一个硅晶片的主表面 到至少一个主表面。 然而，由于当焊接在一起时由于凸起和焊盘的位移而存在差的电耦合的问题。 本发明通过进行硅晶片的临时定位来解决这样的问题，通过诸如能够通过硅晶片的x射线的方法确认位置来确定位置，并且将凸块和 一边通过热压而使设置在硅晶片的主表面之间的层间粘合剂硬化。

公开(公告)号：US20110104852A1

公开(公告)日：2011-05-05

申请号：US13005350

申请日：2011-01-12

申请人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US20090294990A1

公开(公告)日：2009-12-03

申请号：US12537723

申请日：2009-08-07

申请人： Masakazu ISHINO ,  Hiroaki IKEDA ,  Kayoko SHIBATA

发明人： Masakazu ISHINO ,  Hiroaki IKEDA ,  Kayoko SHIBATA

IPC分类号： H01L23/52

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。