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24 条记录 (耗时 0.024 秒)

    Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4956693A

    公开(公告)日：1990-09-11

    申请号：US28140

    申请日：1987-03-19

    申请人： Yasuo Sawahata ,  Ryuichi Saito ,  Naohiro Momma

    发明人： Yasuo Sawahata ,  Ryuichi Saito ,  Naohiro Momma

    IPC分类号： H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

    CPC分类号： H01L21/26506 ,  H01L21/74 ,  H01L29/1079 ,  H01L29/167

    摘要： Disclosed is a semiconductor device having a support region, an element-forming region (e.g., an epitaxial layer) and a buried layer between the support region and the element-forming region, with at least one of a MOS element and a bipolar element being formed in the element-forming region. The feature of the present invention resides in that atoms of at least one element selected from oxygen, nitrogen, carbon, argon, neon, krypton and helium is contained in a layer in at least one of the element-forming region and the buried layer, so as to suppress auto-doping of impurities from the buried layer into the element-forming region and suppress swelling of the buried layer.

    摘要翻译： 公开了一种在支撑区域和元件形成区域之间具有支撑区域，元件形成区域（例如，外延层）和掩埋层的半导体器件，其中MOS元件和双极元件中的至少一个为 形成在元件形成区域中。 本发明的特征在于，选自氧，氮，碳，氩，氖，氪和氦中的至少一种元素的原子包含在元素形成区域和掩埋层中的至少一个中的层中， 从而抑制杂质从掩埋层自动掺杂到元件形成区域并抑制埋层的溶胀。

    Water cooled inverter
    4.
    发明授权
    Water cooled inverter 有权
    水冷变频器

    公开(公告)号：US06621701B2

    公开(公告)日：2003-09-16

    申请号：US10195561

    申请日：2002-07-16

    申请人： Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

    发明人： Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

    IPC分类号： H05H720

    CPC分类号： H05K7/20927 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/00

    摘要： According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

    摘要翻译： 根据本发明，提供一种在壳体中形成多个浅空腔和深腔的水冷逆变器结构，将功率半导体模块的底表面固定到浅腔，以形成浅水通道并直接冷却功率半导体模块 使用这个浅水通道。 由于冷却水在浅水通道中快速流动，所以可以提高冷却效率，并且还可以使用具有深空腔的深水通道来减少压力损失。 此外，提供多个空腔使得可以减小功率半导体模块的尺寸并提供多个功率半导体模块，从而提高可靠性。 可以在水通道下方设置控制板，以将功率半导体模块的控制板热切断，从而可以降低控制电路的温度。

    Water cooled inverter
    5.
    发明授权
    Water cooled inverter 有权

    公开(公告)号：US06661659B2

    公开(公告)日：2003-12-09

    申请号：US10100012

    申请日：2002-03-19

    申请人： Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

    发明人： Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

    IPC分类号： H05H720

    CPC分类号： H05K7/20927 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/00

    摘要： According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

    Stacked MOS transistor flip-flop memory cell
    8.
    发明授权
    Stacked MOS transistor flip-flop memory cell 失效
    堆叠MOS晶体管触发器存储单元

    公开(公告)号：US4894801A

    公开(公告)日：1990-01-16

    申请号：US77176

    申请日：1987-07-24

    申请人： Ryuichi Saito ,  Naohiro Momma

    发明人： Ryuichi Saito ,  Naohiro Momma

    IPC分类号： G11C11/41 ,  H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/11

    摘要： A semiconductor memory including two cross-coupled driver MOS transistors respectively having source and drain regions within a semiconductor substrate and each of the drain regions being in ohmic contact with the gate electrode of the other driver MOS transistor. The gate electrodes of the driver MOS transistors are formed in a first-level polycrystalline silicon (polysilicon) layer and the two transfer MOS transistors respectively have their source and drain regions formed in portions of a second-level polysilicon layer. The driver regions are formed so as to be independently brought into ohmic contact with the respective drain regions of the driver MOS transistors, and each of the transfer MOS transistors have a gate electrode effected in a third-level polysilicon layer which also defines a word line. Two load resistors are respectively formed in those regions of the second-level polysilicon layer which extend from the drain regions of the transfer MOS transistors to a power supply potential line, and wherein the corresponding regions of the load resistors are connected to the power supply potential line in the second-level polysilicon layer. Two metallic data lines are respectively brought into ohmic contact with the source regions of the two transfer MOS transistors and wherein the ground wirings of the memory cell are respectively defined by extending portions of the source regions of the two driver MOS transistors.

    摘要翻译： 一种半导体存储器，包括分别在半导体衬底内具有源极和漏极区域的两个交叉耦合的驱动器MOS晶体管，并且每个漏极区域与另一个驱动器MOS晶体管的栅电极欧姆接触。 驱动器MOS晶体管的栅电极形成在第一级多晶硅（多晶硅）层中，并且两个转移MOS晶体管分别具有形成在二级多晶硅层的一部分中的源极和漏极区域。 形成驱动器区域以独立地与驱动器MOS晶体管的漏极区域欧姆接触，并且每个传输MOS晶体管都具有在第三级多晶硅层中实现的栅电极，该第三级多晶硅层还限定字线 。 分别在从传输MOS晶体管的漏极区域延伸到电源电位线的第二级多晶硅层的那些区域中分别形成两个负载电阻器，并且其中负载电阻器的相应区域连接到电源电位 线在二级多晶硅层。 两个金属数据线分别与两个传输MOS晶体管的源极区域欧姆接触，并且其中存储单元的接地布线分别通过延伸两个驱动器MOS晶体管的源极区域的部分来限定。

    Semiconductor pressure sensor and pressure sensing device
    9.
    发明申请
    Semiconductor pressure sensor and pressure sensing device 审中-公开
    半导体压力传感器和压力传感装置

    公开(公告)号：US20050132814A1

    公开(公告)日：2005-06-23

    申请号：US11049872

    申请日：2005-02-04

    申请人： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

    发明人： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

    IPC分类号： B81B3/00 ,  B81B7/00 ,  G01L7/08 ,  G01L9/00 ,  H01L21/00

    CPC分类号： B81C1/00333 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00293 ,  B81C2203/0145 ,  G01L9/0042 ,  G01L9/0073

    摘要： The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, there by sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film. This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

    摘要翻译： 本发明的目的是提出一种蚀刻通道密封结构，其特征在于对根据牺牲层蚀刻技术制造的压力传感器中的防潮性和抗隔膜的时间变化具有优异的防渗性，并且提供了一种特征在于优异的压力传感器 生产力和耐久性。 在通过牺牲层蚀刻技术形成非常小的间隙之后，通过密封蚀刻通道，通过CVD技术等沉积氧化硅膜。 此外，形成多晶硅等的不渗透性薄膜以覆盖氧化物膜。 这允许在根据牺牲层蚀刻技术产生的压力传感器中简化蚀刻通道密封结构，并且防止水分进入空腔，从而改善耐湿性。 此外，具有小膜应力的密封材料减小了隔膜的时间变形。