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1.发明申请Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects 有权使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法公开(公告)号：US20050064660A1
公开(公告)日：2005-03-24
申请号：US10968233
申请日：2004-10-19
IPC分类号： H01L21/283 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/44
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。 还提供了制造集成电路器件的相关方法。
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2.发明授权Integrated circuit devices that utilize doped Poly-Si1−xGex conductive plugs as interconnects 有权利用掺杂的Poly-Si1-xGex导电插头作为互连的集成电路器件公开(公告)号：US06828616B2
公开(公告)日：2004-12-07
申请号：US10012116
申请日：2001-11-13
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有与衬底表面相邻的第一导电类型的半导体区域。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该装置还包括在接触孔中延伸并与第一导电类型的半导体区域电连接的第一导电类型的多晶Si1-xGex导电插塞。
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公开(公告)号：US06468924B2
公开(公告)日：2002-10-22
申请号：US09871430
申请日：2001-05-31
申请人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
发明人： Seung-hwan Lee , Yeong-kwan Kim , Dong-chan Kim , Young-wook Park
IPC分类号： H01L2131
CPC分类号： H01L21/0228 , C23C16/34 , C23C16/345 , C23C16/402 , C23C16/403 , C23C16/405 , C23C16/409 , C23C16/45531 , C23C16/45542 , H01L21/02164 , H01L21/02178 , H01L21/02183 , H01L21/02186 , H01L21/02194 , H01L21/02197 , H01L21/02274 , H01L21/3185
摘要： Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.
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公开(公告)号：US07544607B2
公开(公告)日：2009-06-09
申请号：US10990429
申请日：2004-11-18
申请人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
发明人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
IPC分类号： H01L21/4763 , H01L29/00 , H01L23/58
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/0228 , H01L21/31612 , H01L21/3185 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823475 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
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5.发明授权Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same 有权具有通过原子层沉积形成的薄膜的半导体器件及其制造方法公开(公告)号：US06833310B2
公开(公告)日：2004-12-21
申请号：US09902607
申请日：2001-07-12
申请人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
发明人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
IPC分类号： H01L2176
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/0228 , H01L21/31612 , H01L21/3185 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823475 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
摘要翻译： 具有通过原子层沉积形成的薄膜的半导体器件及其制造方法，其中所述半导体器件包括形成在沟槽的内壁和底部上的衬垫层，形成在栅堆叠图案功能的侧壁上的栅极间隔 作为栅极线，形成在栅极间隔物和栅极堆叠图案上的第一防止气泡层，形成在用作位线的位线堆叠图案的侧壁上的位线间隔物和形成在位线上的第二防止气泡层 间隔物和栅极堆叠图案，并且上述中的至少一个由氮化硅层和氧化硅层的多层或氧化硅层和氮化硅层的多层形成，从而填充 沟槽，栅极堆叠图案或无空隙的位线堆叠图案。
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6.发明申请Semiconductor device having thin film formed by atomic layer deposition and method for fabricating the same 有权具有通过原子层沉积形成的薄膜的半导体器件及其制造方法公开(公告)号：US20050087828A1
公开(公告)日：2005-04-28
申请号：US10990429
申请日：2004-11-18
申请人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
发明人： Yeong-kwan Kim , Dong-chan Kim , Seung-hwan Lee , Young-wook Park
IPC分类号： H01L21/20 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/76 , H01L31/115
CPC分类号： H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/0228 , H01L21/31612 , H01L21/3185 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823475 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
摘要翻译： 具有通过原子层沉积形成的薄膜的半导体器件及其制造方法，其中所述半导体器件包括形成在沟槽的内壁和底部上的衬垫层，形成在栅堆叠图案功能的侧壁上的栅极间隔 作为栅极线，形成在栅极间隔物和栅极堆叠图案上的第一防止气泡层，形成在用作位线的位线堆叠图案的侧壁上的位线间隔物和形成在位线上的第二防止气泡层 间隔物和栅极堆叠图案，并且上述中的至少一个由氮化硅层和氧化硅层的多层或氧化硅层和氮化硅层的多层形成，从而填充 沟槽，栅极堆叠图案或无空隙的位线堆叠图案。
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7.发明授权Methods of fabricating integrated circuit devices that utilize doped poly-Si1−xGex conductive plugs as interconnects 有权使用掺杂的多晶硅Si-xGex导电插头作为互连的集成电路器件的制造方法公开(公告)号：US07316954B2
公开(公告)日：2008-01-08
申请号：US10968233
申请日：2004-10-19
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L28/60 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
摘要翻译： 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该器件还包括在接触孔中延伸并且电连接到第一导电类型的半导体区域的第一导电类型的多晶Si-1-x-Ge
提供导电类型。 还提供了制造集成电路器件的相关方法。 -
公开(公告)号：US06576053B1
公开(公告)日：2003-06-10
申请号：US09679559
申请日：2000-10-06
申请人： Yeong-kwan Kim , Young-wook Park , Jae-soon Lim , Sung-je Choi , Sang-in Lee
发明人： Yeong-kwan Kim , Young-wook Park , Jae-soon Lim , Sung-je Choi , Sang-in Lee
IPC分类号： C30B2504
CPC分类号： H01L21/31691 , C30B25/02 , C30B29/20 , H01L21/316
摘要： In a method of forming a thin film using an atomic layer deposition (ALD) method, a thin film is formed on a substrate in cycles. Each cycle includes injecting a first reactant including an atom that forms the thin film and a ligand into a reaction chamber that includes the substrate, purging the first reactant, injecting a second reactant into the reaction chamber, and purging the second reactant. The thin film is formed by a chemical reaction between the atom that forms the thin film and a second reactant whose binding energy with respect to the atom that forms the thin film is larger than the binding energy of the ligand with respect to the atom that forms the thin film and the generation of by-products is prevented. The generation of a hydroxide by-product in the thin film is suppressed by using a material that does not include a hydroxide as the second reactant, purging the second reactant, and reacting the second reactant with a third reactant that includes hydroxide. After purging the second reactant, the third reactant for removing impurities and improving the stoichiometry of the thin film is injected and purged. In this way, it is possible to obtain a thin film that does not include impurities and whose stoichiometry is excellent.
摘要翻译： 在使用原子层沉积（ALD）法形成薄膜的方法中，在基板上循环形成薄膜。 每个循环包括将包括形成薄膜的原子和配体的第一反应物注入到包括基板的反应室中，清洗第一反应物，将第二反应物注入反应室，以及清除第二反应物。 薄膜由形成薄膜的原子与第二反应物之间的化学反应形成，第二反应物的结合能相对于形成薄膜的原子的结合能大于配体相对于形成的原子的结合能 防止了薄膜和副产物的产生。 通过使用不包含氢氧化物作为第二反应物的材料，吹扫第二反应物，并使第二反应物与包含氢氧化物的第三反应物反应，可以抑制薄膜中氢氧化物副产物的产生。 在清洗第二反应物之后，注入和清除用于除去杂质的第三反应物和改善薄膜的化学计量。 以这种方式，可以获得不含杂质的化学计量优异的薄膜。
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9.发明授权
公开(公告)号：US6077573A
公开(公告)日：2000-06-20
申请号：US83350
申请日：1998-05-22
申请人： Young-sun Kim , Sang-hyeop Lee , Seung-hwan Lee , Young-wook Park , Mikio Takagi
发明人： Young-sun Kim , Sang-hyeop Lee , Seung-hwan Lee , Young-wook Park , Mikio Takagi
IPC分类号： H01L27/04 , C23C16/24 , H01L21/205 , H01L21/822 , H01L21/8242 , H01L27/108 , H05H1/24
CPC分类号： C23C16/24
摘要： A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.
摘要翻译： 形成微电子器件的方法包括使用等离子体增强化学气相沉积在微电子衬底上形成掺杂杂质的非晶硅层的步骤。 图案化杂质掺杂非晶硅层，使得微电子衬底的部分暴露在图案化的非晶硅层附近。 然后在图案化的非晶硅层上形成半球形的硅层。 此外，形成杂质掺杂非晶硅层的步骤可以在400℃以下的温度下进行。
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公开(公告)号：US06416584B1
公开(公告)日：2002-07-09
申请号：US09350407
申请日：1999-07-08
申请人： Seok-jun Won , Young-wook Park , Yong-woo Hyung
发明人： Seok-jun Won , Young-wook Park , Yong-woo Hyung
IPC分类号： C23C1600
CPC分类号： C23C16/56 , C23C16/405
摘要： An apparatus for forming a film on a substrate includes a reaction chamber and gas supply lines. The gas supply lines supply gases for depositing and annealing the film. Depositing a dielectric film and annealing the dielectric film are performed in situ using the reaction chamber. Thus, the time required for forming the dielectric film is shortened, improving the productivity. Also, deposition and annealing of the dielectric film are performed in the same reaction chamber, so that less area is required for manufacturing equipment.
摘要翻译： 在基板上形成膜的装置包括反应室和气体供给管线。 气体供应管线供应用于沉积和退火膜的气体。 使用反应室原位进行沉积介电膜并退火介电膜。 因此，缩短了形成电介质膜所需的时间，提高了生产率。 此外，电介质膜的沉积和退火在相同的反应室中进行，因此制造设备需要较少的面积。
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