公开(公告)号：US08405213B2

公开(公告)日：2013-03-26

申请号：US12874144

申请日：2010-09-01

Applicant: Chia-Ching Chen ,  Yi-Chuan Ding

Inventor： Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract translation: 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US08278746B2

公开(公告)日：2012-10-02

申请号：US12753837

申请日：2010-04-02

Applicant: Yi-Chuan Ding ,  Chia-Ching Chen

Inventor： Yi-Chuan Ding ,  Chia-Ching Chen

IPC: H01L25/065 ,  H01L23/52 ,  H01L21/70 ,  H01L23/48

CPC classification number: H01L23/3107 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

Abstract translation: 这里描述的是具有堆叠功能和相关的堆叠封装组件和方法的晶片级半导体器件封装。 在一个实施例中，半导体器件封装包括一组邻近一组堆叠半导体器件的周边设置的连接元件。 至少一个连接元件被引线接合到堆叠的半导体器件的上部的有源表面。

公开(公告)号：US20110241193A1

公开(公告)日：2011-10-06

申请号：US12753840

申请日：2010-04-02

Applicant: Yi-Chuan Ding ,  Chia-Ching Chen

Inventor： Yi-Chuan Ding ,  Chia-Ching Chen

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

Abstract translation: 半导体器件封装的实施例包括：（1）包括图案化导电层的互连单元; （2）从导电层基本垂直延伸的电互连; （3）与所述互连单元相邻并且电连接到所述导电层的半导体器件; （4）包装体;（a）基本上覆盖所述互连单元和所述装置的上表面; 和（b）限定与所述包装体的上表面相邻的开口并暴露所述互连件的上表面; 以及（5）电连接到所述装置的连接元件，基本上填充所述开口并暴露在所述装置封装的外周边。 互连的上表面限定了由互连单元的上表面的至少一部分限定的第二平面上方的第一平面，并且在由封装主体的上表面限定的第三平面之下。

公开(公告)号：US20130171774A1

公开(公告)日：2013-07-04

申请号：US13776567

申请日：2013-02-25

Applicant: Chia-Ching Chen ,  Yi-Chuan Ding

Inventor： Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract translation: 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US20110241192A1

公开(公告)日：2011-10-06

申请号：US12753837

申请日：2010-04-02

Applicant: Yi-Chuan Ding ,  Chia-Ching Chen

Inventor： Yi-Chuan Ding ,  Chia-Ching Chen

IPC: H01L25/065 ,  H01L23/52 ,  H01L21/70 ,  H01L23/48

CPC classification number: H01L23/3107 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

Abstract translation: 这里描述的是具有堆叠功能和相关的堆叠封装组件和方法的晶片级半导体器件封装。 在一个实施例中，半导体器件封装包括一组邻近一组堆叠半导体器件的周边设置的连接元件。 至少一个连接元件被引线接合到堆叠的半导体器件的上部的有源表面。

公开(公告)号：US20110227220A1

公开(公告)日：2011-09-22

申请号：US12874144

申请日：2010-09-01

Applicant: Chia-Ching Chen ,  Yi-Chuan Ding

Inventor： Chia-Ching Chen ,  Yi-Chuan Ding

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

Abstract: A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

Abstract translation: 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US08624374B2

公开(公告)日：2014-01-07

申请号：US12753840

申请日：2010-04-02

Applicant: Yi-Chuan Ding ,  Chia-Ching Chen

Inventor： Yi-Chuan Ding ,  Chia-Ching Chen

IPC: H01L23/02

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

Abstract: An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

Abstract translation: 半导体器件封装的实施例包括：（1）包括图案化导电层的互连单元; （2）从导电层基本垂直延伸的电互连; （3）与所述互连单元相邻并且电连接到所述导电层的半导体器件; （4）包装体;（a）基本上覆盖所述互连单元和所述装置的上表面; 和（b）限定与所述包装体的上表面相邻的开口并暴露所述互连件的上表面; 以及（5）电连接到所述装置的连接元件，基本上填充所述开口并暴露在所述装置封装的外周边。 互连的上表面限定了由互连单元的上表面的至少一部分限定的第二平面上方的第一平面，并且在由封装主体的上表面限定的第三平面之下。

公开(公告)号：US20130276639A1

公开(公告)日：2013-10-24

申请号：US13452938

申请日：2012-04-23

Applicant: Chia-Ching Chen

Inventor： Chia-Ching Chen

IPC: A47J31/44 ,  A47J31/06

CPC classification number: A47J31/20

Abstract: A portable cup for brewing includes a cup. A bottom of the cup is defined as a bottom cap. A receiving space is defined on the upper surface of the bottom cap. A food product is received in the receiving space. A soluble edible gum seals the receiving space. Wherein, the food product is fully protected by the soluble edible gum from exposing in the air for preserving the food product from corrupt.

Abstract translation: 用于冲泡的便携式杯包括杯子。 杯的底部被定义为底盖。 在底盖的上表面上限定接收空间。 在接收空间接收食品。 可溶性食用胶密封接收空间。 其中食品完全受到可溶性食用胶的保护，不会在空气中露出，以保护食品免受腐败。

公开(公告)号：US20120130964A1

公开(公告)日：2012-05-24

申请号：US13299243

申请日：2011-11-17

Applicant: Show-Jane YEN ,  Chia-Ching Chen ,  Yue-Shi Lee

Inventor： Show-Jane YEN ,  Chia-Ching Chen ,  Yue-Shi Lee

IPC: G06F17/30 ,  G06F7/00

CPC classification number: G06Q30/02 ,  G06Q10/0637

Abstract: The present invention discloses a fast algorithm for mining high utility itemsets, wherein some transaction data and item utilities are recorded in a tree structure. The method to construct a tree structure is recording on a node the item utilities appearing from the root node to the node. Some techniques are used to reduce the mining space, whereby the fast algorithm can directly generate high utility itemsets from the tree structure without generating any candidates. The fast algorithm of the present invention is more efficient than the existing highest-efficiency algorithm. The present invention further proposes a compression method to effectively save memory space.

Abstract translation: 本发明公开了一种用于挖掘高效用项集的快速算法，其中一些事务数据和项目实用程序以树结构记录。 构建树结构的方法是在节点上记录从根节点到节点出现的项目实用程序。 一些技术用于减少挖掘空间，因此快速算法可以直接从树结构生成高效用项集，而不产生任何候选。 本发明的快速算法比现有的最高效率算法更有效。 本发明还提出了一种有效地节省存储空间的压缩方法。

公开(公告)号：USD539192S1

公开(公告)日：2007-03-27

申请号：US29246695

申请日：2006-05-04

Applicant: Chia-Ching Chen ,  Jung-Chung Chen

Designer： Chia-Ching Chen ,  Jung-Chung Chen