公开(公告)号：US08624374B2

公开(公告)日：2014-01-07

申请号：US12753840

申请日：2010-04-02

申请人： Yi-Chuan Ding ,  Chia-Ching Chen

发明人： Yi-Chuan Ding ,  Chia-Ching Chen

IPC分类号： H01L23/02

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

摘要： An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

摘要翻译： 半导体器件封装的实施例包括：（1）包括图案化导电层的互连单元; （2）从导电层基本垂直延伸的电互连; （3）与所述互连单元相邻并且电连接到所述导电层的半导体器件; （4）包装体;（a）基本上覆盖所述互连单元和所述装置的上表面; 和（b）限定与所述包装体的上表面相邻的开口并暴露所述互连件的上表面; 以及（5）电连接到所述装置的连接元件，基本上填充所述开口并暴露在所述装置封装的外周边。 互连的上表面限定了由互连单元的上表面的至少一部分限定的第二平面上方的第一平面，并且在由封装主体的上表面限定的第三平面之下。

公开(公告)号：US20110227220A1

公开(公告)日：2011-09-22

申请号：US12874144

申请日：2010-09-01

申请人： Chia-Ching Chen ,  Yi-Chuan Ding

发明人： Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

摘要： A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

摘要翻译： 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US20130171774A1

公开(公告)日：2013-07-04

申请号：US13776567

申请日：2013-02-25

申请人： Chia-Ching Chen ,  Yi-Chuan Ding

发明人： Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L21/50

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

摘要： A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

摘要翻译： 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US20110241192A1

公开(公告)日：2011-10-06

申请号：US12753837

申请日：2010-04-02

申请人： Yi-Chuan Ding ,  Chia-Ching Chen

发明人： Yi-Chuan Ding ,  Chia-Ching Chen

IPC分类号： H01L25/065 ,  H01L23/52 ,  H01L21/70 ,  H01L23/48

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

摘要翻译： 这里描述的是具有堆叠功能和相关的堆叠封装组件和方法的晶片级半导体器件封装。 在一个实施例中，半导体器件封装包括一组邻近一组堆叠半导体器件的周边设置的连接元件。 至少一个连接元件被引线接合到堆叠的半导体器件的上部的有源表面。

公开(公告)号：US08405213B2

公开(公告)日：2013-03-26

申请号：US12874144

申请日：2010-09-01

申请人： Chia-Ching Chen ,  Yi-Chuan Ding

发明人： Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

摘要： A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

摘要翻译： 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。

公开(公告)号：US08278746B2

公开(公告)日：2012-10-02

申请号：US12753837

申请日：2010-04-02

申请人： Yi-Chuan Ding ,  Chia-Ching Chen

发明人： Yi-Chuan Ding ,  Chia-Ching Chen

IPC分类号： H01L25/065 ,  H01L23/52 ,  H01L21/70 ,  H01L23/48

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

摘要翻译： 这里描述的是具有堆叠功能和相关的堆叠封装组件和方法的晶片级半导体器件封装。 在一个实施例中，半导体器件封装包括一组邻近一组堆叠半导体器件的周边设置的连接元件。 至少一个连接元件被引线接合到堆叠的半导体器件的上部的有源表面。

公开(公告)号：US20110241193A1

公开(公告)日：2011-10-06

申请号：US12753840

申请日：2010-04-02

申请人： Yi-Chuan Ding ,  Chia-Ching Chen

发明人： Yi-Chuan Ding ,  Chia-Ching Chen

IPC分类号： H01L23/538 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

摘要： An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body.

摘要翻译： 半导体器件封装的实施例包括：（1）包括图案化导电层的互连单元; （2）从导电层基本垂直延伸的电互连; （3）与所述互连单元相邻并且电连接到所述导电层的半导体器件; （4）包装体;（a）基本上覆盖所述互连单元和所述装置的上表面; 和（b）限定与所述包装体的上表面相邻的开口并暴露所述互连件的上表面; 以及（5）电连接到所述装置的连接元件，基本上填充所述开口并暴露在所述装置封装的外周边。 互连的上表面限定了由互连单元的上表面的至少一部分限定的第二平面上方的第一平面，并且在由封装主体的上表面限定的第三平面之下。

公开(公告)号：US07091583B2

公开(公告)日：2006-08-15

申请号：US10933349

申请日：2004-09-03

申请人： Ying-Chih Chen ,  Yun-Hsiang Tien ,  Ming-Jiun Lai ,  Yi-Chuan Ding

发明人： Ying-Chih Chen ,  Yun-Hsiang Tien ,  Ming-Jiun Lai ,  Yi-Chuan Ding

IPC分类号： H01L23/02

CPC分类号： H01L24/97 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/60 ,  H01L2223/54473 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/0269 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/06 ,  H05K3/242 ,  H05K3/28 ,  H05K2201/09918 ,  H05K2203/0574 ,  H05K2203/175 ,  H01L2924/00

摘要： The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer. By removing the exposed portion of the plating bus, the breaking hole is formed to electrically isolate the extended trail from the contact pads in order to prevent a chip on the substrate strip from being damaged by ESD (Electrostatic Discharge) during packaging processes.

摘要翻译： 本发明提供了一种用于防止衬底条的泄漏的结构和方法。 衬底条包括边缘部分和多个单元。 衬底条表面上的图案化金属层包括延伸到边缘部分的至少一个电镀母线，在该单元处的多条电镀线，在该单元处的多个接触焊盘和在边缘部分处的多个基准标记 。 电镀母线具有一个伸出的线，其一端暴露在衬底带的侧壁外。 基准标记和接触垫从焊料掩模的多个第一开口露出。 焊接掩模还在边缘部分处具有暴露电镀总线的一部分以限定断裂孔的第二开口。 在基准标记和接触焊盘上形成表面层之后，电镀总线的露出部分没有表面层。 通过去除电镀总线的暴露部分，形成断开孔以将延伸的迹线与接触焊盘电隔离，以防止在封装过程中ESD（静电放电）在衬底条上的芯片被损坏。

公开(公告)号：US06528882B2

公开(公告)日：2003-03-04

申请号：US09849137

申请日：2001-05-04

申请人： Yi-Chuan Ding ,  Chang-Chi Lee ,  Kun-Ching Chen ,  Yung-I Yeh

发明人： Yi-Chuan Ding ,  Chang-Chi Lee ,  Kun-Ching Chen ,  Yung-I Yeh

IPC分类号： H01L2334

CPC分类号： H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

公开(公告)号：US07125745B2

公开(公告)日：2006-10-24

申请号：US10833087

申请日：2004-04-28

申请人： Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

发明人： Kun-Ching Chen ,  Yi-Chuan Ding ,  Po-Jen Cheng ,  Chih-Ming Chung ,  Yun-Hsiang Tien

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

摘要翻译： 用于倒装芯片凸块和引线接合应用的多芯片封装衬底包括具有顶表面和底表面的衬底本体。 多个凸台和多个引线接合垫形成在顶表面上。 凸起垫设置在基板主体的顶表面上，并且在凸起的焊盘上形成预焊材料。 引线接合焊盘设置在基板主体的顶表面上，并且在引线接合焊盘上形成Ni / Au层。 为了避免在包装过程中碰撞垫和引线接合垫发生氧化。 预焊材料完全覆盖凸块，以避免在包装过程中在凸起芯片上的多个凸块中产生的Au金属间化合物。 用于倒装芯片凸块和引线接合应用的多芯片堆叠封装的可靠性将大大提高。