公开(公告)号：US07745244B2

公开(公告)日：2010-06-29

申请号：US12144289

申请日：2008-06-23

申请人： Zhongfa Yuan ,  Yong Liu ,  Yumin Liu ,  Qiuxiao Qian

发明人： Zhongfa Yuan ,  Yong Liu ,  Yumin Liu ,  Qiuxiao Qian

IPC分类号： H01L21/00

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y10T29/49158 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

摘要翻译： 半导体管芯封装。 封装的实施例可以包括具有整个布置的固体导电针的衬底。 半导体管芯可以附接到衬底的表面。 可以通过固体导电针提供与半导体管芯的电连接。

公开(公告)号：US20090256245A1

公开(公告)日：2009-10-15

申请号：US12102799

申请日：2008-04-14

申请人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu ,  Zhongfa Yuan

发明人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu ,  Zhongfa Yuan

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49562 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H02M3/155 ,  H01L2224/05599

摘要： Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe.

摘要翻译： 公开了半导体管芯封装，制造所述封装的方法和使用所述封装的系统。 包括至少一个半导体管芯的示例性封装，该半导体管芯设置在引线框架的一个表面上并电耦合到引线框架的至少一个导电区域，以及至少一个无源电气部件，其布置在引线框架的另一个表面上并至少电耦合 引线框架的一个导电区域。

公开(公告)号：US20090315171A1

公开(公告)日：2009-12-24

申请号：US12144289

申请日：2008-06-23

申请人： Zhongfa Yuan ,  Yong Liu ,  Yumin Liu ,  Qiuxiao Qian

发明人： Zhongfa Yuan ,  Yong Liu ,  Yumin Liu ,  Qiuxiao Qian

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L23/52 ,  H01L21/44 ,  H01K3/22

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2203/0235 ,  Y10T29/49158 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

摘要翻译： 半导体管芯封装。 封装的实施例可以包括具有整个布置的固体导电引脚的基板。 半导体管芯可以附接到衬底的表面。 可以通过固体导电针提供与半导体管芯的电连接。

公开(公告)号：US08421204B2

公开(公告)日：2013-04-16

申请号：US13110865

申请日：2011-05-18

申请人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

发明人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/185 ,  H01L2924/00

摘要： Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding.

摘要翻译： 公开了由嵌入式半导体芯片和电气部件的模块构成的半导体管芯封装。 在一个实施例中，半导体管芯封装包括第一模块和连接到第一模块的第二模块。 一个或多个半导体裸片嵌入在第一模块中，并且一个或多个电组件，例如表面安装组件，嵌入在第二模块中。 第一模块可以通过层压工艺形成，并且第二模块可以通过层压工艺或模制工艺形成。 图案化的金属层和通孔提供对封装以及芯片和封装的部件之间的电互连。 第二模块可以通过将单独制造的模块的互连焊盘彼此连接，或者可以通过层压或模制来直接附接到第一模块。

公开(公告)号：US20120292778A1

公开(公告)日：2012-11-22

申请号：US13110865

申请日：2011-05-18

申请人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

发明人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/185 ,  H01L2924/00

摘要： Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding.

摘要翻译： 公开了由嵌入式半导体芯片和电气部件的模块构成的半导体管芯封装。 在一个实施例中，半导体管芯封装包括第一模块和连接到第一模块的第二模块。 一个或多个半导体裸片嵌入在第一模块中，并且一个或多个电组件，例如表面安装组件，嵌入在第二模块中。 第一模块可以通过层压工艺形成，并且第二模块可以通过层压工艺或模制工艺形成。 图案化的金属层和通孔提供对封装以及芯片和封装的部件之间的电互连。 第二模块可以通过将单独制造的模块的互连焊盘彼此连接，或者可以通过层压或模制来直接附接到第一模块。

公开(公告)号：US20130005083A9

公开(公告)日：2013-01-03

申请号：US13397285

申请日：2012-02-15

申请人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  Jung Tae Lee ,  Luke Huiyong Chung

发明人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  Jung Tae Lee ,  Luke Huiyong Chung

IPC分类号： H01L21/56

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

公开(公告)号：US08138585B2

公开(公告)日：2012-03-20

申请号：US12128130

申请日：2008-05-28

申请人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  JungTae Lee ,  Huiyong Luke Chung

发明人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  JungTae Lee ,  Huiyong Luke Chung

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

摘要翻译： 包括100个的模制的无引线封装半导体多芯片模块具有用于全桥电路的四个mosfet 10,12,14,16。 MOSFET可以包括两个N沟道和两个P沟道器件或四个相同类型的MOS器件，但是优选四个N沟道。 在模块100中，存在用于组装mosfet的两个引线框30,40。 特别地，两个N沟道和两个P沟道器件设置在两个引线框之间并封装在电绝缘的模制化合物84中。所得到的封装具有四个上部散热器44.1-44.4，其暴露在模制化合物84中用于转移 从mosfet到周围环境的热量。 不需要引线键。 这可以显着降低RDSON的导通电阻。 顶部或源极 - 漏极引线框架30可以焊接到桥式MOSFET的源极和栅极。

公开(公告)号：US07829988B2

公开(公告)日：2010-11-09

申请号：US12235227

申请日：2008-09-22

申请人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian

发明人： Yong Liu ,  Howard Allen ,  Qiuxiao Qian

IPC分类号： H01L21/50

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49861 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/19105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads.

摘要翻译： 公开了可以与用于半导体管芯的引线框一样薄的预成型部件封装，使用其的系统及其制造方法。 示例性包装的引线在引线框架的两个表面处露出。 封装可以彼此堆叠并且在引线的暴露部分处电耦合。

公开(公告)号：US20090194887A1

公开(公告)日：2009-08-06

申请号：US12026742

申请日：2008-02-06

申请人： Yong Liu ,  Qiuxiao Qian

发明人： Yong Liu ,  Qiuxiao Qian

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

公开(公告)号：US08367481B2

公开(公告)日：2013-02-05

申请号：US13397285

申请日：2012-02-15

申请人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  JungTae Lee ,  Luke Huiyong Chung

发明人： Yong Liu ,  Qiuxiao Qian ,  JiangYuan Zhang ,  Mike Speed ,  JungTae Lee ,  Luke Huiyong Chung

IPC分类号： H01L21/56

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

摘要翻译： 包括100个的模制的无引线封装半导体多芯片模块具有用于全桥电路的四个mosfet 10,12,14,16。 MOSFET可以包括两个N沟道和两个P沟道器件或四个相同类型的MOS器件，但是优选四个N沟道。 在模块100中，存在用于组装mosfet的两个引线框30,40。 特别地，两个N沟道和两个P沟道器件设置在两个引线框之间并封装在电绝缘的模制化合物84中。所得到的封装具有四个上部散热器44.1-44.4，其暴露在模制化合物84中用于转移 从mosfet到周围环境的热量。 不需要引线键。 这可以显着降低RDSON的导通电阻。 顶部或源极 - 漏极引线框架30可以焊接到桥式MOSFET的源极和栅极。