公开(公告)号：US4357470A

公开(公告)日：1982-11-02

申请号：US256780

申请日：1981-04-23

申请人： Yoshiaki Watanabe ,  Chihiro Yokoo ,  Toshifumi Asaka ,  Akira Onodera ,  Kaoru Sota ,  Jiro Sawada

发明人： Yoshiaki Watanabe ,  Chihiro Yokoo ,  Toshifumi Asaka ,  Akira Onodera ,  Kaoru Sota ,  Jiro Sawada

IPC分类号： C07D519/06 ,  A61K31/545 ,  A61P31/04 ,  C07D471/04 ,  C07D501/26 ,  C07D501/36 ,  C07D501/56

CPC分类号： C07D471/04

摘要： Novel cephalosporin compounds having the general formula ##STR1## wherein X represents hydrogen atom or hydroxy group, and the non-toxic pharmacologically acceptable salts thereof are disclosed. These compounds are useful as antibacterial agents.

摘要翻译： 公开了具有通式 + TR 的新型头孢菌素化合物，其中X表示氢原子或羟基，并且其无毒的药理学上可接受的盐被公开。 这些化合物可用作抗菌剂。

公开(公告)号：US4190581A

公开(公告)日：1980-02-26

申请号：US929566

申请日：1978-07-31

申请人： Yoshiaki Watanabe ,  Chihiro Yokoo ,  Toshifumi Asaka ,  Jiro Sawada

发明人： Yoshiaki Watanabe ,  Chihiro Yokoo ,  Toshifumi Asaka ,  Jiro Sawada

IPC分类号： C07D241/42 ,  C07D471/04 ,  C07D499/00 ,  C07D499/68 ,  C07D499/50 ,  C07D401/04

CPC分类号： C07D471/04 ,  C07D241/42 ,  C07D499/00

摘要： Novel penicillin derivatives of the formula ##STR1## and pharmaceutically acceptable salts thereof, wherein R is hydrogen or hydroxy, are produced by acylating ampicillin, amoxicillin or a salt thereof with 4-hydroxy-pyrazino[2,3-f]quinoline-3-carboxylic acid or its functional derivative. They have high anti-pseudomonas activity and other antibacterial activity against gram-positive and gram-negative bacteria, and are of extremely low toxicity.

摘要翻译： 通过用4-羟基 - 吡嗪并[2,3-f]将氨苄青霉素，阿莫西林或其盐酰化来制备其中R为氢或羟基的新颖的式 + TR 及其药学上可接受的盐的青霉素衍生物 ]喹啉-3-羧酸或其官能衍生物。 它们对革兰氏阳性和革兰氏阴性细菌具有很高的抗假单胞菌活性和其他抗菌活性，毒性极低。

公开(公告)号：US4150240A

公开(公告)日：1979-04-17

申请号：US813989

申请日：1977-07-08

申请人： Kaoru Sota ,  Toshihisa Ogawa ,  Jiro Sawada

发明人： Kaoru Sota ,  Toshihisa Ogawa ,  Jiro Sawada

IPC分类号： C07C319/02 ,  C07C67/00 ,  C07C313/00 ,  C07C323/58 ,  C07C99/00

摘要： D-Penicillamine and salts thereof may be prepared by reacting certain aryl amines with 4-thiazolidinecarboxylic acid compounds obtained by splitting the .beta.-lactam ring of penicillin derivatives such as benzylpenicillin or phenoxymethylpenicillin.

摘要翻译： D-青霉胺及其盐可以通过使某些芳基胺与通过分解青霉素衍生物例如苄青霉素或苯氧基甲基青霉素的β-内酰胺环获得的4-噻唑烷羧酸化合物反应来制备。

公开(公告)号：US4472316A

公开(公告)日：1984-09-18

申请号：US469000

申请日：1983-02-23

申请人： Kaoru Sota ,  Yasuhide Tachi ,  Kazuyuki Tomisawa ,  Kazuya Kameo ,  Toru Matsunaga ,  Jiro Sawada

发明人： Kaoru Sota ,  Yasuhide Tachi ,  Kazuyuki Tomisawa ,  Kazuya Kameo ,  Toru Matsunaga ,  Jiro Sawada

IPC分类号： A61K31/215 ,  A61K31/19 ,  A61P9/10 ,  C07C59/84 ,  C07C67/00 ,  C07C313/00 ,  C07C323/56 ,  C07C327/20 ,  C07C327/22 ,  C07C149/43 ,  C07C153/01

CPC分类号： C07C59/84 ,  C07C323/00 ,  C07C327/00

摘要： Novel compounds having the general formula ##STR1## wherein X is hydrogen or halogen, Y is hydrogen, halogen, methoxy or alkyl having 1 to 3 carbon atoms, Z is hydrogen, alkylcarbonyl having 2 to 6 carbon atoms or benzoyl, and R is hydrogen, alkali metal or alkyl having 1 to 5 carbon atoms, are disclosed. These compounds exhibit excellent hypolipidemic activity and little or no side effect.

摘要翻译： 具有通式的新型化合物，其中X为氢或卤素，Y为氢，卤素，甲氧基或具有1至3个碳原子的烷基，Z为氢，具有2至6个碳原子的烷基羰基或苯甲酰基，R为氢 ，碱金属或具有1至5个碳原子的烷基。 这些化合物表现出优异的降血脂活性，很少或没有副作用。

公开(公告)号：US20060120125A1

公开(公告)日：2006-06-08

申请号：US11330220

申请日：2006-01-12

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C19/08

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

公开(公告)号：US06657901B2

公开(公告)日：2003-12-02

申请号：US10254980

申请日：2002-09-26

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C1604

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

摘要翻译： 一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由横截面划分的四个区域中。 外围电路布置在芯片的中心部分的这种结构的好处是，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的意图。 存储容量。

公开(公告)号：US06515913B2

公开(公告)日：2003-02-04

申请号：US10000032

申请日：2001-12-04

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C1604

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

公开(公告)号：US20070242535A1

公开(公告)日：2007-10-18

申请号：US11714867

申请日：2007-03-07

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C7/10

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

摘要翻译： 形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。 半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。 第一存储器阵列形成在第一矩形区域中。 第二存储器阵列形成在第二矩形区域中。 电压发生器和第一接合焊盘布置在第三矩形区域中。 第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。

公开(公告)号：US6160744A

公开(公告)日：2000-12-12

申请号：US361203

申请日：1999-07-27

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C11/34 ,  G11C11/406 ,  H01L23/485 ,  G11C13/00

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C11/406 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

公开(公告)号：US5602771A

公开(公告)日：1997-02-11

申请号：US159621

申请日：1993-12-01

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C11/34 ,  G11C11/406 ,  H01L23/485

CPC分类号： G11C5/025 ,  G11C11/406 ,  G11C5/063 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025

摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

摘要翻译： 这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由 交叉区域。 由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。