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    Methods of manufacturing semiconductor devices having self-aligned contact pads
    1.
    发明授权
    Methods of manufacturing semiconductor devices having self-aligned contact pads 有权
    制造具有自对准接触焊盘的半导体器件的方法

    公开(公告)号：US09184227B1

    公开(公告)日：2015-11-10

    申请号：US14529500

    申请日：2014-10-31

    申请人： Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    发明人： Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    IPC分类号： H01L21/336 ,  H01L49/02 ,  H01L21/8234

    CPC分类号： H01L27/10823 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7827

    摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

    摘要翻译： 半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极， 所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽， 相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构 线路和相应接触焊盘上的电容器的下电极。

    Semiconductor devices having self-aligned contact pads
    2.
    发明授权
    Semiconductor devices having self-aligned contact pads 有权
    具有自对准接触焊盘的半导体器件

    公开(公告)号：US09240414B1

    公开(公告)日：2016-01-19

    申请号：US14875396

    申请日：2015-10-05

    申请人： Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    发明人： Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    IPC分类号： H01L21/336 ,  H01L27/108 ,  H01L29/78 ,  H01L29/423

    CPC分类号： H01L27/10823 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7827

    摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

    摘要翻译： 半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极， 所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽， 相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构 线路和相应接触焊盘上的电容器的下电极。

    SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME 有权
    具有自对准接触垫的半导体器件及其制造方法

    公开(公告)号：US20150311276A1

    公开(公告)日：2015-10-29

    申请号：US14529500

    申请日：2014-10-31

    申请人： YOUNG-KUK KIM ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    发明人： YOUNG-KUK KIM ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    IPC分类号： H01L49/02 ,  H01L21/8234

    CPC分类号： H01L27/10823 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7827

    摘要： A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

    摘要翻译： 半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极， 所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽， 相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构 线路和相应接触焊盘上的电容器的下电极。

    Semiconductor device and fabricating method thereof
    4.
    发明授权
    Semiconductor device and fabricating method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09287270B2

    公开(公告)日：2016-03-15

    申请号：US14279301

    申请日：2014-05-15

    申请人： Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    发明人： Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    IPC分类号： H01L27/108 ,  H01L49/02

    CPC分类号： H01L27/10805 ,  H01L27/10808 ,  H01L27/1085 ,  H01L28/91

    摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

    摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有圆柱形状的存储电极，形成在存储电极上的电介质膜和形成在电介质膜上的平板电极，其中该平板电极包括一个第一半导体化合物层和第二半导体化合物层， 另一方面，第一半导体化合物层的结晶度与第二半导体化合物层的结晶度不同。

    High performance MIS capacitor with HfO2 dielectric
    6.
    发明授权
    High performance MIS capacitor with HfO2 dielectric 失效
    具有HfO2电介质的高性能MIS电容器

    公开(公告)号：US07094712B2

    公开(公告)日：2006-08-22

    申请号：US10793818

    申请日：2004-03-08

    申请人： Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

    发明人： Ki-Vin Im ,  Ki-Yeon Park ,  Jae-Hyun Yeo ,  In-Sung Park ,  Seung-Hwan Lee ,  Young-Sun Kim ,  Sung-Tae Kim

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0228 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： Disclosed is a method for forming metal oxide dielectric layers, more particularly HfO2 dielectric layers, using an atomic layer deposition (ALD) method in which a series of thin intermediate layers are formed and treated with one or more oxidizers and nitrogents before the next intermediate layer is formed on the substrate. The intermediate oxidation treatments reduce the number of organic contaminants incorporated into the metal oxide layer from the organometallic precursors to produce a dielectric layer having improved current leakage characteristics. The dielectric layers formed in this manner remain susceptible to crystallization if exposed to temperatures much above 550° C., so subsequent semiconductor manufacturing processes should be modified or eliminated to avoid such temperatures or limit the duration at such temperatures to maintain the performance of the dielectric materials.

    摘要翻译： 公开了一种使用原子层沉积（ALD）方法形成金属氧化物电介质层，更具体地是HfO 2 电介质层的方法，其中形成一系列薄的中间层并用一个或多个 在下一个中间层之前形成氧化剂和氮。 中间氧化处理减少了从有机金属前体引入到金属氧化物层中的有机污染物的数量，以产生具有改善的电流泄漏特性的电介质层。 如果暴露在高于550℃的温度下，以这种方式形成的电介质层仍然易于结晶，因此随后的半导体制造工艺应当被修改或消除以避免这种温度或限制在这样的温度下的持续时间以保持电介质的性能 材料