公开(公告)号：US20130015872A1

公开(公告)日：2013-01-17

申请号：US13184008

申请日：2011-07-15

申请人： Yun-Han Lee ,  Mill-Jer Wang ,  Tan-Li Chou

发明人： Yun-Han Lee ,  Mill-Jer Wang ,  Tan-Li Chou

IPC分类号： G01R1/073 ,  G01R31/20

CPC分类号： G01R1/07385

摘要： A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

摘要翻译： 探针卡包括多个探针，以及连接到多个探针的开关网络。 开关网络被配置为以第一模式连接多个探针，并且以与第一图案不同的第二图案重新连接多个探针。

公开(公告)号：US08860448B2

公开(公告)日：2014-10-14

申请号：US13184008

申请日：2011-07-15

申请人： Yun-Han Lee ,  Mill-Jer Wang ,  Tan-Li Chou

发明人： Yun-Han Lee ,  Mill-Jer Wang ,  Tan-Li Chou

IPC分类号： G01R31/20 ,  G01R1/073

CPC分类号： G01R1/07385

摘要： A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

摘要翻译： 探针卡包括多个探针，以及连接到多个探针的开关网络。 开关网络被配置为以第一模式连接多个探针，并且以与第一图案不同的第二图案重新连接多个探针。

公开(公告)号：US09704766B2

公开(公告)日：2017-07-11

申请号：US13118201

申请日：2011-05-27

申请人： Sandeep Kumar Goel ,  Mill-Jer Wang ,  Chung-Sheng Yuan ,  Tom Chen ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee

发明人： Sandeep Kumar Goel ,  Mill-Jer Wang ,  Chung-Sheng Yuan ,  Tom Chen ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee

IPC分类号： H01L23/48 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L22/32 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00

摘要： An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

公开(公告)号：US09817029B2

公开(公告)日：2017-11-14

申请号：US13313228

申请日：2011-12-07

申请人： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

发明人： Mill-Jer Wang ,  Ching-Fang Chen ,  Sandeep Kumar Goel ,  Chung-Sheng Yuan ,  Chao-Yang Yeh ,  Chin-Chou Liu ,  Yun-Han Lee ,  Hung-Chih Lin

IPC分类号： G01R1/067 ,  G01R1/073

CPC分类号： G01R1/07342 ,  G01R1/07378 ,  H01L2224/16225

摘要： A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

公开(公告)号：US09310437B2

公开(公告)日：2016-04-12

申请号：US13072325

申请日：2011-03-25

申请人： Chun-Cheng Chen ,  Hung-Chih Lin ,  Mill-Jer Wang ,  Hao Chen ,  Ching-Nen Peng

发明人： Chun-Cheng Chen ,  Hung-Chih Lin ,  Mill-Jer Wang ,  Hao Chen ,  Ching-Nen Peng

IPC分类号： G01R31/02 ,  G01R31/319 ,  G01R31/3183 ,  G01R31/3185

CPC分类号： G01R31/31919 ,  G01R31/318371 ,  G01R31/318511

摘要： A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.

摘要翻译： 一种方法包括测试彼此相同并包括集成电路的第一设备和第二设备。 根据第一装置的第一测试顺序执行第一装置的测试，其中第一测试序列包括多个有序测试项目，并且其中第一测试序列包括测试项目。 基于与具有与第一装置相同的结构的多个装置的测试中的测试项目的失败频率来计算测试项目的测试优先级。 然后调整第一测试序列以响应于测试项目的测试优先级产生第二测试序列，其中第二测试序列与第一测试序列不同。 根据第二个测试顺序对第二个设备进行测试。

公开(公告)号：US08956889B2

公开(公告)日：2015-02-17

申请号：US13800626

申请日：2013-03-13

申请人： Hung-Chih Lin ,  Mill-Jer Wang ,  Ching-Nen Peng ,  Hao Chen

发明人： Hung-Chih Lin ,  Mill-Jer Wang ,  Ching-Nen Peng ,  Hao Chen

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.

摘要翻译： 在通过衬底上的互连测试多个通过硅通孔（TSV）连接在一起的方法中，将测试信号施加到多个测试焊盘中的第一测试焊盘，并且在第二测试焊盘处测量返回信号 在多个测试焊盘之间。 多个测试焊盘中的至少一个测试焊盘接地到基板。 多个测试焊盘的剩余测试焊盘或者连接到多个链接的TSV或接地。

公开(公告)号：US08836355B2

公开(公告)日：2014-09-16

申请号：US13082769

申请日：2011-04-08

申请人： Mill-Jer Wang ,  Ching Nen Peng ,  Hung-Chih Lin ,  Hao Chen

发明人： Mill-Jer Wang ,  Ching Nen Peng ,  Hung-Chih Lin ,  Hao Chen

IPC分类号： G01R31/10 ,  G01R31/28

CPC分类号： G01R31/287 ,  G01R31/2856 ,  G01R31/2863 ,  G01R31/2874 ,  G01R31/2875

摘要： A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

摘要翻译： 建立了堆叠系统中的模具的多组测试条件，其中多个测试条件是模具的温度的函数，并且其中堆叠的系统包括多个堆叠的模具。 测量模具的温度。 从多组测试条件中可以找到相应的模具测试条件，其中该组测试条件对应于温度。 模具在使用一组测试条件的温度下产生测试结果。

公开(公告)号：US20130147049A1

公开(公告)日：2013-06-13

申请号：US13313907

申请日：2011-12-07

申请人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen

发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen

IPC分类号： H01L23/52 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/544 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/1712 ,  H01L2224/81193 ,  H01L2225/06596

摘要： A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.

公开(公告)号：US08421073B2

公开(公告)日：2013-04-16

申请号：US13006639

申请日：2011-01-14

申请人： Hung-Chih Lin ,  Mill-Jer Wang ,  Ching-Nen Peng ,  Hao Chen

发明人： Hung-Chih Lin ,  Mill-Jer Wang ,  Ching-Nen Peng ,  Hao Chen

IPC分类号： H01L23/58

CPC分类号： H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.

摘要翻译： 衬底上或三维集成电路（3DIC）中的多个穿通硅通孔（TSV）被链接在一起。 TSV链接在一起以增加电信号。 使用多个测试垫来实现TVS的测试。 其中一个测试焊盘接地。 剩余的测试焊盘或者电连接到链条中的TSV或接地。

公开(公告)号：US20120242346A1

公开(公告)日：2012-09-27

申请号：US13053951

申请日：2011-03-22

申请人： Mill-Jer Wang ,  Ching Nen Peng ,  Hung-Chih Lin ,  Hao Chen

发明人： Mill-Jer Wang ,  Ching Nen Peng ,  Hung-Chih Lin ,  Hao Chen

IPC分类号： G01R31/02

CPC分类号： G01R31/318513 ,  G01R31/2886

摘要： A device, such as a 3DIC stacked device includes a first device under test (DUT) connected to a first force pad by a first through substrate via (TSV) stack and connected to a first sense pad by a second TSV stack. The device further includes a second DUT stacked above the first DUT and connected to a second force pad and a second force pad by a second third TSV and connected to a second sense pad by a fourth TSV. Functional blocks on either the first or second blocks can be accessed for testing by way of the TSVs. In some applications the TSVs are vertically aligned to form TSV stacks.

摘要翻译： 诸如3DIC堆叠设备的设备包括被第一通过衬底经由（TSV）堆叠连接到第一力垫的第一被测设备（DUT），并且通过第二TSV堆叠连接到第一感测焊盘。 该装置还包括堆叠在第一DUT上方的第二DUT，并通过第二个第三TSV连接到第二强制焊盘和第二受力垫，并通过第四TSV连接到第二传感焊盘。 可以访问第一或第二块上的功能块，以便通过TSV进行测试。 在一些应用中，TSV被垂直对准以形成TSV堆叠。