公开(公告)号：US20120214259A1

公开(公告)日：2012-08-23

申请号：US13213458

申请日：2011-08-19

申请人： Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

发明人： Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

IPC分类号： H01L21/66

CPC分类号： G01N23/2258 ,  G01N2223/611

摘要： Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film.

摘要翻译： 经验表明，在含氧作为主要成分的材料中，相对于化学计量组成等的痕量氧的过量或不足影响材料的性能。 氧化膜层叠体的氧扩散评价方法包括以下步骤：测量包含第一氧化物膜和第二氧化物膜的基板的氧同位素的定量值，所述氧化物存在比例与氧同位素 通过二次离子质谱法在深度方向上在第一氧化膜中的氧同位素的存在比例; 并评估从第一氧化物膜扩散到第二氧化物膜的氧同位素中的一种。

公开(公告)号：US08450123B2

公开(公告)日：2013-05-28

申请号：US13213458

申请日：2011-08-19

申请人： Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

发明人： Yutaka Okazaki ,  Keitaro Imai ,  Atsuo Isobe ,  Shunpei Yamazaki

IPC分类号： H01L21/66

CPC分类号： G01N23/2258 ,  G01N2223/611

摘要： Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film.

摘要翻译： 经验表明，在含氧作为主要成分的材料中，相对于化学计量组成等的痕量氧的过量或不足影响材料的性能。 氧化膜层叠体的氧扩散评价方法包括以下步骤：测量包含第一氧化物膜和第二氧化物膜的基板的氧同位素的定量值，所述氧化物存在比例与氧同位素 通过二次离子质谱法在深度方向上在第一氧化膜中的氧同位素的存在比例; 并评估从第一氧化物膜扩散到第二氧化物膜的氧同位素中的一种。

公开(公告)号：US08748889B2

公开(公告)日：2014-06-10

申请号：US13188992

申请日：2011-07-22

申请人： Toshinari Sasaki ,  Hitomi Sato ,  Kosei Noda ,  Yuta Endo ,  Mizuho Ikarashi ,  Keitaro Imai ,  Atsuo Isobe ,  Yutaka Okazaki

发明人： Toshinari Sasaki ,  Hitomi Sato ,  Kosei Noda ,  Yuta Endo ,  Mizuho Ikarashi ,  Keitaro Imai ,  Atsuo Isobe ,  Yutaka Okazaki

IPC分类号： H01L29/12 ,  H01L21/36

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606

摘要： It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.

摘要翻译： 本发明的目的是制造其中包括氧化物半导体的晶体管具有常态特性，电特性波动小，可靠性高的半导体器件。 首先，在基板上进行第一热处理，在基板上形成基极绝缘层，在基底绝缘层上形成氧化物半导体层，对形成氧化物半导体的工序进行第一热处理的工序 在不暴露于空气的情况下执行层。 接下来，在形成氧化物半导体层之后，进行第二热处理。 使用通过加热而释放氧的绝缘层作为基底绝缘层。

公开(公告)号：US08581309B2

公开(公告)日：2013-11-12

申请号：US13277489

申请日：2011-10-20

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

IPC分类号： H01L27/092

CPC分类号： H01L27/1266 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/433 ,  H01L23/481 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/7843 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/16152 ,  H01L2924/16195

摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

摘要翻译： 目的是在具有SOI结构的半导体器件中实现高性能和低功耗。 此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。 半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。 通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和 可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

公开(公告)号：US08044464B2

公开(公告)日：2011-10-25

申请号：US12209739

申请日：2008-09-12

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

IPC分类号： H01L27/01

CPC分类号： H01L27/1266 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/433 ,  H01L23/481 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/7843 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/16152 ,  H01L2924/16195

摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

摘要翻译： 目的是在具有SOI结构的半导体器件中实现高性能和低功耗。 此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。 半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。 通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管与 可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

公开(公告)号：US07982250B2

公开(公告)日：2011-07-19

申请号：US12209696

申请日：2008-09-12

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo ,  Yutaka Okazaki

IPC分类号： H01L27/12

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2224/80001

摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.

摘要翻译： 示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。 多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。 多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。 此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

公开(公告)号：US08569753B2

公开(公告)日：2013-10-29

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

发明人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC分类号： H01L21/02

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US08952379B2

公开(公告)日：2015-02-10

申请号：US13608044

申请日：2012-09-10

申请人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromachi Godo ,  Takehisa Hatano ,  Sachiaki Tezuka ,  Suguru Hondo ,  Naoto Yamade ,  Junichi Koezuka

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromachi Godo ,  Takehisa Hatano ,  Sachiaki Tezuka ,  Suguru Hondo ,  Naoto Yamade ,  Junichi Koezuka

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a semiconductor device in which an oxide semiconductor layer is provided; a pair of wiring layers which are provided with the gate electrode layer interposed therebetween are electrically connected to the low-resistance regions; and electrode layers are provided to be in contact with the low-resistance regions, below regions where the wiring layers are formed.

摘要翻译： 提供一种半导体器件，其中提供氧化物半导体层; 设置有栅极电极层的一对布线层电连接到低电阻区域; 并且电极层设置成与低电阻区域接触，在形成布线层的区域之下。

公开(公告)号：US08343816B2

公开(公告)日：2013-01-01

申请号：US12850652

申请日：2010-08-05

申请人： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

发明人： Ryota Imahayashi ,  Shinobu Furukawa ,  Atsuo Isobe ,  Yasuyuki Arai ,  Shunpei Yamazaki

IPC分类号： H01L21/00

CPC分类号： H01L51/0512 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/31683 ,  H01L51/0002 ,  H01L51/0055 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0566

摘要： It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

摘要翻译： 本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。 本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜 电子密度为1011cm -3以上的等离子体，等离子体活化时电子温度为0.2eV〜2.0eV的范围，直接与成为要被绝缘的栅电极的导体层的一部分反应。

公开(公告)号：US07718547B2

公开(公告)日：2010-05-18

申请号：US12334589

申请日：2008-12-15

申请人： Atsuo Isobe ,  Satoshi Murakami ,  Tamae Takano ,  Shunpei Yamazaki

发明人： Atsuo Isobe ,  Satoshi Murakami ,  Tamae Takano ,  Shunpei Yamazaki

IPC分类号： H01L21/31

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384

摘要： A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm−3 or more and 1×1013 cm−3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.

摘要翻译： 本发明的半导体器件的制造方法包括以下步骤：在衬底上形成第一绝缘膜，在第一绝缘膜上形成半导体膜，通过对半导体膜进行等离子体处理来对半导体膜进行氧化或氮化 使用高频波，电子密度为1×10 11 cm -3以上且1×10 13 cm -3以下且电子温度为0.5eV以上1.5eV以下的条件，形成第2绝缘膜 覆盖半导体膜，在第二绝缘膜上形成栅电极，形成第三绝缘膜以覆盖栅电极，并在第三绝缘膜上形成导电膜。