公开(公告)号：US5122045A

公开(公告)日：1992-06-16

申请号：US698159

申请日：1991-05-09

申请人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

发明人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

IPC分类号： H01L31/02 ,  H01L23/50 ,  H01L31/0203 ,  H01L43/00 ,  H01S5/022 ,  H05K3/34

CPC分类号： H01L33/62 ,  G01J1/0403 ,  H01L31/0203 ,  H01L33/54 ,  H01S5/02216 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01S5/02228 ,  Y02P70/613 ,  Y10S425/228

摘要： A mold for molding a semiconductor package including a semiconductor chip mounted on a lead frame, wherein a major surface of the semiconductor chip is inclined relative to a surface of the semiconductor package, the mold includes a first mold half including a first mold cavity having a first mold surface and at least four first side surfaces, a second mold half including a second mold cavity having a second main surface extending substantially parallel to the first main surface and at least four second side surfaces extending substantially perpendicular to the second main surface, and a portion for supporting the lead frame and the semiconductor chip in the first and second mold cavities and position the major surface of the semiconductor chip in an inclined position relative to the second main surface, wherein the portion for supporting and positioning includes a first mating surface on the first mold half inclined relative to the first main surface and a second mating surface on the second mold half inclined relative to the second main surface.

公开(公告)号：US5025305A

公开(公告)日：1991-06-18

申请号：US517294

申请日：1990-05-01

申请人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

发明人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

IPC分类号： H01L31/02 ,  H01L23/50 ,  H01L31/0203 ,  H01L43/00 ,  H01S5/022 ,  H05K3/34

CPC分类号： H01L33/62 ,  G01J1/0403 ,  H01L31/0203 ,  H01L33/54 ,  H01S5/02216 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01S5/02228 ,  Y02P70/613 ,  Y10S425/228

摘要： A semiconductor device for detecting or emitting a magnetic line of force or light is so provided that the major surface of its built-in semiconductor chip has a predetermined inclination angle relative to a mount surface of a mount substrate. An active layer of element for detecting a magnetic line of force or light or an element for emitting a magnetic line of force or light is formed on the major surface of the semiconductor chip. It is, therefore, possible to achieve a smaller mount thickness as defined relative to a mount surface and to detect a magnetic line of force or light coming in a direction parallel to the mount surface or to emit a magnetic line of force or light in a direction vertical to the mount surface.

公开(公告)号：US4972241A

公开(公告)日：1990-11-20

申请号：US234652

申请日：1988-08-22

申请人： Toshikazu Fukuda ,  Toru Suga ,  Yutaka Tomisawa

发明人： Toshikazu Fukuda ,  Toru Suga ,  Yutaka Tomisawa

IPC分类号： H01L43/02 ,  H01L43/00 ,  H01L43/06 ,  H01L43/14

CPC分类号： H01L43/14 ,  H01L43/06 ,  H01L43/065

摘要： A chip including a Hall element for detecting a magnetic force is p repared. On the chip is formed an unhardened magnetic resin layer, which is formed of a mixture of soft magnetic powder an dsilicone rubber. The unhardened magnetic resin layer is applied with a magnetic field and is stretched in a direction perpendicular to one face of the chip, so that its top portion is formed in a substantially conical shape and its bottom portion is formed in a substantially rectangular block, the ratio of the length Wa of its base to its height Wb, Wb/Wa, being equal to or greater than 1. The magnetic resin layer is then hardened. As a result, a magnetic force detecting semiconductor device is provided, which has a magnetic resin layer with a high magnetic force convergence that has its top portion formed in a conical shape and its bottom portion formed in a rectangular block, the ratio of the length of its base to its height being equal to and greater than 1.

公开(公告)号：US4814284A

公开(公告)日：1989-03-21

申请号：US111288

申请日：1987-10-22

申请人： Kazuhiko Inoue ,  Yutaka Tomisawa

发明人： Kazuhiko Inoue ,  Yutaka Tomisawa

IPC分类号： H01L21/329 ,  H01L21/76 ,  H01L29/93 ,  H01L21/265 ,  H01L29/91

CPC分类号： H01L29/66174 ,  H01L21/7605 ,  H01L29/93

摘要： A GaAs planar diode includes an N type GaAs substrate having an N.sup.+ GaAs layer on which an N.sup.- GaAs layer is formed. A first impurity layer of the N.sup.+ type is formed on the N.sup.31 GaAs layer. A second impurity layer of a p.sup.+ type is formed on the first impurity layer, wherein a p-n junction is formed between the first and second impurity layers. A semi-insulation region, for encompassing a predetermined area of the p-n junction of the first and second impurity layers, is formed in the substrate. The depth of the semi-insulation region in the substrate is deeper than the total depth of the first and second impurity layers, so that the semi-insulation region serves as an element isolation region of the p-n junction of the first and second impurity layers.

摘要翻译： GaAs平面二极管包括具有形成有N-GaAs层的N + GaAs层的N型GaAs衬底。 在N31 GaAs层上形成N +型的第一杂质层。 在第一杂质层上形成p +型第二杂质层，其中在第一和第二杂质层之间形成p-n结。 在衬底中形成用于包围第一和第二杂质层的p-n结的预定区域的半绝缘区域。 衬底中的半绝缘区域的深度比第一和第二杂质层的总深度深，使得半绝缘区域用作第一和第二杂质层的p-n结的元件隔离区域。

公开(公告)号：US4775878A

公开(公告)日：1988-10-04

申请号：US60341

申请日：1987-06-10

申请人： Kazuhiko Inoue ,  Yutaka Tomisawa

发明人： Kazuhiko Inoue ,  Yutaka Tomisawa

IPC分类号： H01L23/12 ,  H01L21/338 ,  H01L27/02 ,  H01L29/10 ,  H01L29/812 ,  H01L29/80

CPC分类号： H01L27/0218 ,  H01L29/1075 ,  H01L29/812 ,  H01L2224/48247 ,  H01L2224/48257

摘要： Disclosed is a semiconductor device having a field effect transistor (FET) formed in a semi-insulative substrate. A positive bias voltage equal to or higher than the bias voltage applied to the drain electrode of the FET is applied to a back surface electrode formed on the back surface of the substrate, with the result that the electrons generated within the semi-insulative substrate are pulled into the back surface electrode so as to prevent said electrons from flowing into the drain region and, thus, to prevent the drain current vibration.

摘要翻译： 公开了一种半导体器件，其具有形成在半绝缘衬底中的场效应晶体管（FET）。 施加到施加到FET的漏电极的偏置电压以上的正偏置电压被施加到形成在衬底的背面上的背面电极，结果是在半绝缘衬底内产生的电子为 拉入背面电极，以防止所述电子流入漏极区域，从而防止漏电流振动。

公开(公告)号：US5065204A

公开(公告)日：1991-11-12

申请号：US602933

申请日：1990-10-25

申请人： Yutaka Tomisawa ,  Tetsuo Ishii ,  Kazuhiko Inoue

发明人： Yutaka Tomisawa ,  Tetsuo Ishii ,  Kazuhiko Inoue

IPC分类号： H01L43/06 ,  G01R33/06 ,  G01R33/07 ,  H01L29/82

CPC分类号： H01L29/82 ,  G01R33/06

摘要： A novel magnetoelectric element and a novel magnetoelectric apparatus convert a magnetic field into an electric capacitance and output it by utilizing the Lorentz force acting on a current in the magnetic field. The magnetoelectric element can convert a magnetic field into an electric capacitance and output it. The magnetoelectric apparatus includes the magnetoelectric element and an electric capacitance detecting unit, and can output a magnetic field as a change in frequency.

公开(公告)号：US4680569A

公开(公告)日：1987-07-14

申请号：US654940

申请日：1984-09-27

申请人： Bunshiro Yamaki ,  Sadatake Kikuchi ,  Yutaka Tomisawa

发明人： Bunshiro Yamaki ,  Sadatake Kikuchi ,  Yutaka Tomisawa

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/0084 ,  G01L19/147

摘要： A semiconductor pressure sensor wherein a semiconductor chip of diaphragm type is supported by a mount plate through a thin tubular supporting member or a pressure inlet tube having a coefficient of thermal expansion similar to that of a substrate constituting the semiconductor chip. The semiconductor chip is fixed to the thin tubular supporting member or the pressure inlet tube by means of a bonding material, and the thin tubular supporting member or the pressure inlet tube is fixed by means of a bonding material having a high bonding strength with respect thereto, thus absorbing thermal stress produced due to the difference in coefficient of thermal expansion.

摘要翻译： 一种半导体压力传感器，其中隔膜型半导体芯片通过薄管状支撑构件或具有类似于构成半导体芯片的衬底的热膨胀系数的压力入口管由安装板支撑。 半导体芯片通过接合材料固定在薄管状支撑构件或压力入口管上，薄壁管状支撑构件或压力入口管借助于相对于其的高粘合强度的接合材料固定 ，从而吸收由于热膨胀系数的差异而产生的热应力。

公开(公告)号：US4187514A

公开(公告)日：1980-02-05

申请号：US848569

申请日：1977-11-04

申请人： Yutaka Tomisawa ,  Tatsuro Mitani

发明人： Yutaka Tomisawa ,  Tatsuro Mitani

IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L21/761 ,  H01L29/45 ,  H01L29/808

CPC分类号： H01L29/808 ,  H01L21/761 ,  H01L29/456 ,  Y10S148/124

摘要： A junction type field effect transistor comprising a semiconductor substrate; semiconductor regions formed in the semiconductor substrate and exposed on a major surface thereof, the semiconductor regions including a gate region and an isolation region; and a polycrystalline semiconductor layer formed on the surface of the gate region or on the surfaces of the gate region and the isolation region. The polycrystalline semiconductor layer contains an impurity of the same conductivity type as the gate and the isolation regions.

摘要翻译： 一种包括半导体衬底的结型场效应晶体管; 半导体区域形成在半导体衬底中并在其主表面上暴露，所述半导体区域包括栅极区域和隔离区域; 以及形成在栅极区域的表面上或栅极区域和隔离区域的表面上的多晶半导体层。 多晶半导体层含有与栅极和隔离区相同导电类型的杂质。

公开(公告)号：US4267557A

公开(公告)日：1981-05-12

申请号：US44402

申请日：1979-06-01

申请人： Ken-ichi Muramoto ,  Keizo Tani ,  Yutaka Tomisawa ,  Makoto Hideshima

发明人： Ken-ichi Muramoto ,  Keizo Tani ,  Yutaka Tomisawa ,  Makoto Hideshima

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73

CPC分类号： H01L29/0821 ,  H01L29/0626 ,  H01L29/1004 ,  H01L29/7302

摘要： A junction type semiconductor device, wherein a protective diode is formed in a part of the region consisting of a base region and a collector region. The device permits reducing the manufacturing cost of semiconductor elements, makes it possible to provide a smaller electric apparatus, and is high in reliability.

摘要翻译： 一种结型半导体器件，其中在由基极区域和集电极区域构成的区域的一部分中形成保护二极管。 该装置允许降低半导体元件的制造成本，使得可以提供更小的电气设备，并且可靠性高。