公开(公告)号：US5122045A

公开(公告)日：1992-06-16

申请号：US698159

申请日：1991-05-09

申请人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

发明人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

IPC分类号： H01L31/02 ,  H01L23/50 ,  H01L31/0203 ,  H01L43/00 ,  H01S5/022 ,  H05K3/34

CPC分类号： H01L33/62 ,  G01J1/0403 ,  H01L31/0203 ,  H01L33/54 ,  H01S5/02216 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01S5/02228 ,  Y02P70/613 ,  Y10S425/228

摘要： A mold for molding a semiconductor package including a semiconductor chip mounted on a lead frame, wherein a major surface of the semiconductor chip is inclined relative to a surface of the semiconductor package, the mold includes a first mold half including a first mold cavity having a first mold surface and at least four first side surfaces, a second mold half including a second mold cavity having a second main surface extending substantially parallel to the first main surface and at least four second side surfaces extending substantially perpendicular to the second main surface, and a portion for supporting the lead frame and the semiconductor chip in the first and second mold cavities and position the major surface of the semiconductor chip in an inclined position relative to the second main surface, wherein the portion for supporting and positioning includes a first mating surface on the first mold half inclined relative to the first main surface and a second mating surface on the second mold half inclined relative to the second main surface.

公开(公告)号：US5025305A

公开(公告)日：1991-06-18

申请号：US517294

申请日：1990-05-01

申请人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

发明人： Yutaka Tomisawa ,  Toshikazu Fukuda ,  Kazuhiko Inoue

IPC分类号： H01L31/02 ,  H01L23/50 ,  H01L31/0203 ,  H01L43/00 ,  H01S5/022 ,  H05K3/34

CPC分类号： H01L33/62 ,  G01J1/0403 ,  H01L31/0203 ,  H01L33/54 ,  H01S5/02216 ,  H05K3/3426 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01S5/02228 ,  Y02P70/613 ,  Y10S425/228

摘要： A semiconductor device for detecting or emitting a magnetic line of force or light is so provided that the major surface of its built-in semiconductor chip has a predetermined inclination angle relative to a mount surface of a mount substrate. An active layer of element for detecting a magnetic line of force or light or an element for emitting a magnetic line of force or light is formed on the major surface of the semiconductor chip. It is, therefore, possible to achieve a smaller mount thickness as defined relative to a mount surface and to detect a magnetic line of force or light coming in a direction parallel to the mount surface or to emit a magnetic line of force or light in a direction vertical to the mount surface.

公开(公告)号：US4972241A

公开(公告)日：1990-11-20

申请号：US234652

申请日：1988-08-22

申请人： Toshikazu Fukuda ,  Toru Suga ,  Yutaka Tomisawa

发明人： Toshikazu Fukuda ,  Toru Suga ,  Yutaka Tomisawa

IPC分类号： H01L43/02 ,  H01L43/00 ,  H01L43/06 ,  H01L43/14

CPC分类号： H01L43/14 ,  H01L43/06 ,  H01L43/065

摘要： A chip including a Hall element for detecting a magnetic force is p repared. On the chip is formed an unhardened magnetic resin layer, which is formed of a mixture of soft magnetic powder an dsilicone rubber. The unhardened magnetic resin layer is applied with a magnetic field and is stretched in a direction perpendicular to one face of the chip, so that its top portion is formed in a substantially conical shape and its bottom portion is formed in a substantially rectangular block, the ratio of the length Wa of its base to its height Wb, Wb/Wa, being equal to or greater than 1. The magnetic resin layer is then hardened. As a result, a magnetic force detecting semiconductor device is provided, which has a magnetic resin layer with a high magnetic force convergence that has its top portion formed in a conical shape and its bottom portion formed in a rectangular block, the ratio of the length of its base to its height being equal to and greater than 1.

公开(公告)号：US4784718A

公开(公告)日：1988-11-15

申请号：US16770

申请日：1987-02-19

申请人： Tatsuro Mitani ,  Toshikazu Fukuda

发明人： Tatsuro Mitani ,  Toshikazu Fukuda

IPC分类号： H01L29/872 ,  H01L21/338 ,  H01L29/47 ,  H01L29/812 ,  H01L21/00 ,  B44C1/22 ,  C03C15/00 ,  H01L21/306

CPC分类号： H01L29/66871

摘要： Disclosed is a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate, and with its source/drain heavily doped regions, which are formed by doping Se in a lightly doped semiconductor layer on the GaAs substrate, self-aligned with both gate electrode and source/drain extraction electrodes.

摘要翻译： 公开了一种半导体器件，其栅电极和源极/漏极引出电极由GaAs衬底上的相同材料制成，并且其源极/漏极重掺杂区域通过将掺杂Se掺入到轻掺杂半导体层中而形成 GaAs衬底，与栅极电极和源极/漏极引出电极自对准。

公开(公告)号：US08030713B2

公开(公告)日：2011-10-04

申请号：US12401698

申请日：2009-03-11

申请人： Takayuki Hiraoka ,  Toshikazu Fukuda

发明人： Takayuki Hiraoka ,  Toshikazu Fukuda

IPC分类号： H01L27/088

CPC分类号： H01L21/823418 ,  H01L21/823412 ,  H01L27/0251 ,  H01L27/088 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/7848

摘要： A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

摘要翻译： 未形成硅锗层的硅锗非形成区域和形成有硅锗层的硅锗形成区域设置在硅芯片中，内部电路和输入/输出缓冲器布置在硅 - 锗形成区域，以及焊盘电极和静电保护元件布置在硅 - 锗非形成区域中。

公开(公告)号：US4603130A

公开(公告)日：1986-07-29

申请号：US594298

申请日：1984-03-28

申请人： Ryuichi Iemura ,  Tsuneo Kawashima ,  Toshikazu Fukuda ,  Keizo Ito ,  Takashi Nose ,  Goro Tsukamoto

发明人： Ryuichi Iemura ,  Tsuneo Kawashima ,  Toshikazu Fukuda ,  Keizo Ito ,  Takashi Nose ,  Goro Tsukamoto

IPC分类号： A61K31/415 ,  A61K31/4184 ,  A61K31/55 ,  A61P43/00 ,  C07D235/14 ,  C07D403/06 ,  C07D403/04 ,  A61K31/495 ,  C07D241/02

CPC分类号： C07D235/14 ,  Y02P20/55

摘要： Novel benzimidazole derivatives of the formula: ##STR1## wherein R.sup.1 is a lower alkyl group, a lower alkenyl group or a lower alkynyl group, R.sup.2 is hydrogen atom, a lower alkyl group or a lower hydroxyalkyl group, and n is 2 or 3, or a pharmaceutically acceptable acid addition salt thereof, which have potent antihistaminic activity with less toxicity and hence are useful as an antihistaminics, and a process for the preparation of the compounds, and a pharmaceutical composition useful as antihistaminics containing the compound as an essential active ingredient.

摘要翻译： 下式的新型苯并咪唑衍生物：其中R1是低级烷基，低级烯基或低级炔基，R2是氢原子，低级烷基或低级羟烷基，n是2或3， 或其药学上可接受的酸加成盐，其具有有效的抗组胺活性，毒性低，因此可用作抗组胺剂，以及用于制备化合物的方法，以及用作抗组胺剂的药物组合物，其含有该化合物作为必需活性成分 。

公开(公告)号：US4430343A

公开(公告)日：1984-02-07

申请号：US436032

申请日：1982-10-22

申请人： Ryuichi Iemura ,  Tsuneo Kawashima ,  Toshikazu Fukuda ,  Keizo Ito ,  Takashi Nose ,  Goro Tsukamoto

发明人： Ryuichi Iemura ,  Tsuneo Kawashima ,  Toshikazu Fukuda ,  Keizo Ito ,  Takashi Nose ,  Goro Tsukamoto

IPC分类号： A61K31/415 ,  A61K31/4184 ,  A61K31/495 ,  A61K31/496 ,  A61K31/55 ,  A61P37/08 ,  A61P43/00 ,  C07D235/24 ,  C07D235/30 ,  C07D403/04 ,  C07D403/02

CPC分类号： C07D235/24 ,  C07D235/30 ,  C07D403/04 ,  Y02P20/55 ,  Y10S514/83 ,  Y10S514/861 ,  Y10S514/914

摘要： Novel benzimidazole derivatives of the formula: ##STR1## wherein R.sup.1 is an alkyl group having 1 to 3 carbon atoms, allyl group, propargyl group, or phenyl group; R.sup.2 is hydrogen atom or an alkyl group having 1 to 3 carbon atoms; and n is 2 or 3, or pharmaceutically acceptable acid addition salts thereof, which have excellent antihistaminic activities and are useful as antiallergics for various allergic diseases, and a process for the preparation thereof, and an antihistaminic composition containing the compound as an active ingredient.

摘要翻译： 具有下式的新型苯并咪唑衍生物：其中R 1是具有1至3个碳原子的烷基，烯丙基，炔丙基或苯基; R2是氢原子或碳原子数1〜3的烷基; 和n为2或3，或其药学上可接受的酸加成盐，其具有优异的抗组胺活性，并且可用作各种过敏性疾病的抗过敏药，及其制备方法，以及含有该化合物作为活性成分的抗组胺组合物。

公开(公告)号：US20120236661A1

公开(公告)日：2012-09-20

申请号：US13237269

申请日：2011-09-20

申请人： Toshikazu Fukuda

发明人： Toshikazu Fukuda

IPC分类号： G11C8/16 ,  G11C7/06

CPC分类号： G11C7/222 ,  G11C11/412

摘要： According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

摘要翻译： 根据一个实施例，当端口A的行地址与端口B的行地址匹配时，仅通过基于第三时钟控制端口A的字线电位而仅从端口A访问存储器单元，并且数据 基于第一时钟在端口A的位线和端口A之间交换数据，并且基于第二时钟在端口A的位线和端口B之间交换数据。

公开(公告)号：US5946962A

公开(公告)日：1999-09-07

申请号：US136422

申请日：1998-08-20

申请人： Toshikazu Fukuda ,  Toshihiro Nakashima

发明人： Toshikazu Fukuda ,  Toshihiro Nakashima

IPC分类号： B21D53/78 ,  B21D53/84 ,  B23P15/00 ,  F16H41/28 ,  B21D28/30

CPC分类号： F16H41/28 ,  B21D53/78 ,  B21D53/84 ,  B23P15/00 ,  Y10T29/4933

摘要： According to the present invention, a turbine shell is manufactured by a method which includes the steps of preparing a planar blank, simultaneously forming a plurality of blade fixture slits 32A, 32B and 32C in the blank 40, and deforming the blank 40 into a curved concave shape by effecting drawing work.

摘要翻译： 根据本发明，通过一种方法制造涡轮壳体，该方法包括以下步骤：制备平面坯料，同时在坯料40中形成多个刀片固定缝32A，32B和32C，并将坯料40变形成弯曲 通过进行绘图工作，形成凹形。

公开(公告)号：US08665636B2

公开(公告)日：2014-03-04

申请号：US13237269

申请日：2011-09-20

申请人： Toshikazu Fukuda

发明人： Toshikazu Fukuda

IPC分类号： G11C11/00

CPC分类号： G11C7/222 ,  G11C11/412

摘要： According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

摘要翻译： 根据一个实施例，当端口A的行地址与端口B的行地址匹配时，仅通过基于第三时钟控制端口A的字线电位而仅从端口A访问存储器单元，并且数据 基于第一时钟在端口A的位线和端口A之间交换数据，并且基于第二时钟在端口A的位线和端口B之间交换数据。