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公开(公告)号:US20220030354A1
公开(公告)日:2022-01-27
申请号:US17495661
申请日:2021-10-06
申请人: Ambiq Micro, Inc.
IPC分类号: H04R3/04 , G06F3/16 , G06F3/01 , G06F40/205
摘要: A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.
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公开(公告)号:US20210104948A1
公开(公告)日:2021-04-08
申请号:US17121593
申请日:2020-12-14
申请人: Ambiq Micro, Inc.
发明人: Ivan Bogue , Yousof Mortazavi
IPC分类号: H02M3/158 , H03K17/0814
摘要: A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.
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公开(公告)号:US10416703B2
公开(公告)日:2019-09-17
申请号:US15674242
申请日:2017-08-10
申请人: Ambiq Micro, Inc.
摘要: A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.
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公开(公告)号:US10347328B2
公开(公告)日:2019-07-09
申请号:US16049078
申请日:2018-07-30
申请人: Ambiq Micro, Inc.
IPC分类号: G11C7/00 , G11C11/419 , G11C11/418 , G11C5/14
摘要: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
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公开(公告)号:US10096354B1
公开(公告)日:2018-10-09
申请号:US15697286
申请日:2017-09-06
申请人: Ambiq Micro, Inc.
IPC分类号: G11C11/00 , G11C11/412 , G11C15/04 , G11C11/56 , G11C16/34
摘要: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
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公开(公告)号:US10062431B2
公开(公告)日:2018-08-28
申请号:US15345229
申请日:2016-11-07
申请人: Ambiq Micro, Inc.
IPC分类号: G11C7/00 , G11C11/419 , G11C11/418
CPC分类号: G11C11/419 , G11C5/147 , G11C11/418
摘要: An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
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公开(公告)号:US20180239415A1
公开(公告)日:2018-08-23
申请号:US15439887
申请日:2017-02-22
申请人: Ambiq Micro, Inc.
发明人: Ivan Bogue , Yanning Lu , Bharath Mandyam
CPC分类号: G06F1/3296 , G05F1/575 , G06F1/26 , G06F1/3243
摘要: A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.
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公开(公告)号:US09939839B2
公开(公告)日:2018-04-10
申请号:US14879863
申请日:2015-10-09
申请人: Ambiq Micro, Inc.
IPC分类号: G06F1/06 , H03L7/06 , H03L7/181 , H03L7/18 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G06F1/32
CPC分类号: G06F1/06 , G01R19/0084 , G05F1/56 , G05F1/575 , G06F1/12 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F11/3041 , G06F11/3414 , G06F13/102 , H02M3/158 , H02M2001/0045 , H03K17/687 , H03L7/00 , H03L7/06 , H03L7/18 , H03L7/181 , H03M1/12 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/14 , Y02D10/171
摘要: A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.
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公开(公告)号:US09939826B2
公开(公告)日:2018-04-10
申请号:US14342177
申请日:2012-06-29
摘要: An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.
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公开(公告)号:US20170287534A1
公开(公告)日:2017-10-05
申请号:US15245016
申请日:2016-08-23
申请人: Ambiq Micro, Inc
IPC分类号: G11C7/14
摘要: A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.
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