公开(公告)号：US20050114635A1

公开(公告)日：2005-05-26

申请号：US11024775

申请日：2004-12-30

申请人： Dong Cho

发明人： Dong Cho

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30145 ,  G06F9/30181

摘要： An instruction decoding unit in a microcomputer is disclosed having an instruction word capable of being selected by a user to conveniently produce application software while maintaining security. The decoding unit in a microcomputer includes an instruction register for storing instructions fetched from a memory, an instruction decoder for decoding instruction codes of the instructions stored in the instruction register and for designating micro-instructions to be executed, a micro-ROM for outputting a series of the micro-instructions designated by the instruction decoder, and a user instruction selector for selecting or changing the micro-instructions of the micro-ROM in response to user's selection so as to change the operation of an instruction word.

公开(公告)号：US20030084921A1

公开(公告)日：2003-05-08

申请号：US10326486

申请日：2002-12-23

申请人： LG Semicon Co., Ltd.

发明人： Yun Jun Huh ,  Suk Bin Han ,  Jae Jeong Kim

IPC分类号： C25F001/00

CPC分类号： H01L21/67057 ,  B08B3/048 ,  B08B3/102 ,  B08B3/12 ,  H01L21/67051 ,  Y10S134/902

摘要： A semiconductor wafer cleaning apparatus comprises an outer tank, a cleaning tank provided within the outer tank, a wafer carrier provided within the cleaning tank, a plurality of jet nozzles directed toward the wafer carrier, a main pipe connected to the jet nozzles, a circulating pump connected to the main pipe and the outer tank for circulating a cleansing solution from the outer tank, through the main pipe, the jet nozzles, and the cleaning tank, and a filter for filtering the circulated cleansing solution.

公开(公告)号：US20020030281A1

公开(公告)日：2002-03-14

申请号：US09946366

申请日：2001-09-06

申请人： LG Semicon Co., Ltd.

发明人： Hyuck-Chai Jung

IPC分类号： H01L023/48

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/76877

摘要： Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures. The method includes the steps of: forming an interlayer insulating structure on the semiconductor device; forming contact holes through the interlayer insulating structure to expose the impurity regions; lining contact-hole-portions of the interlayer insulating layer with portions of a barrier layer, respectively, such that the portions of the barrier layer contact the impurity regions; forming conductive pads on the portions of the barrier layer such that remainders of the contact holes are filled; and forming a wire layer on each one of the conductive pads.

摘要翻译： 公开了一种用于形成用于半导体器件的布线结构的方法，其中形成用于在单元区域中接触的焊盘以及单元宽高比非常高的芯区域和外围区域以及如此形成的导线的结构。 半导体器件包括布置在单元区域和外围和/或芯区域中的半导体衬底，其中外围和/或芯区域在半导体衬底中形成良好，半导体衬底被布置成有源区域和场区域，半导体器件 在场区域中也具有场绝缘层，在有源区域中的半导体衬底的部分上的多个栅极结构以及栅极结构之间的半导体衬底中的杂质区域。 该方法包括以下步骤：在半导体器件上形成层间绝缘结构; 通过所述层间绝缘结构形成接触孔以暴露所述杂质区域; 分别将层间绝缘层的接触孔部分与阻挡层的部分层叠，使得阻挡层的部分与杂质区接触; 在所述阻挡层的所述部分上形成导电焊盘，使得所述接触孔的剩余部分被填充; 以及在每个导电焊盘上形成导线层。

公开(公告)号：US20010017423A1

公开(公告)日：2001-08-30

申请号：US09813834

申请日：2001-03-22

申请人： LG Semicon Co. Ltd.

发明人： Jae Sung Roh ,  Woun S. Yang

IPC分类号： H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC分类号： H01L21/76897 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/823425

摘要： A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.

摘要翻译： 一种在两条栅极线之间形成自对准接触孔的半导体器件及其制造方法。 提供具有形成在其上的第一栅极线的衬底。 在第一栅极线和衬底上形成绝缘体。 然后选择性地去除绝缘体的一部分和第一栅极线的一部分，以将第一栅极线分成第二栅极线和第三栅极线并同时暴露衬底。 因此，在第二和第三栅极线之间产生自对准接触孔。

公开(公告)号：US06166720A

公开(公告)日：2000-12-26

申请号：US66682

申请日：1998-04-28

申请人： Soo-Seok Sim

发明人： Soo-Seok Sim

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/02 ,  H04N9/30 ,  H04N9/67 ,  G09G5/04

CPC分类号： G09G3/3688 ,  G09G5/02 ,  G09G2310/027 ,  H04N9/30 ,  H04N9/67

摘要： YUV to RGB converter for converting a digital YUV signal having a Y signal, a U signal, and a V signal to a digital RGB signal having an R signal, a G signal, and a B signal according to equations:R=Y+N.sub.1 .times.VG=Y-N.sub.2 .times.V-N.sub.3 .times.UB=Y+N.sub.4 .times.Uwherein the YUV to RGB converter performs only bit shifting and adding/subtracting operations, and N.sub.1, N.sub.2, N.sub.3, and N.sub.4 are constants.

摘要翻译： YUV至RGB转换器，用于根据以下等式将具有Y信号，U信号和V信号的数字YUV信号转换为具有R信号，G信号和B信号的数字RGB信号：R = Y + N1×VG = Y-N2xV-N3xUB = Y + N4xU其中YUV到RGB转换器仅执行位移和加法/减法运算，N1，N2，N3和N4是常数。

公开(公告)号：US6137141A

公开(公告)日：2000-10-24

申请号：US69867

申请日：1998-04-30

申请人： Jeong Hwan Son ,  Ki Jae Huh

发明人： Jeong Hwan Son ,  Ki Jae Huh

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/7833 ,  H01L29/66545

摘要： A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process. The present invention is directed most generally to a semiconductor device which includes: a semiconductor substrate of a first conductivity type; a gate insulator on the substrate, the gate insulator sharing an interface with the substrate; a gate electrode on the gate insulator, the gate electrode having a first side, a second side, and a middle region between the first and second sides; a source doped region of a second conductivity type within the substrate to the first side of the gate electrode and a drain doped region of the second conductivity type within the substrate to the second side of the gate electrode, the source and drain doped regions self-aligned to the gate electrode; and a channel doped region of the first conductivity type within the substrate below the gate electrode, the channel doped region having a peak dopant concentration profile such that the peak dopant concentration under the middle region of the gate electrode occurs further below the gate insulator-substrate interface than does either the peak dopant concentration under the first side of the gate electrode or the peak dopant concentration under the second side of the gate electrode.

摘要翻译： 通过离子注入通过非均匀截面的多晶硅栅电极获得沟道区中的不均匀掺杂剂浓度的金属氧化物半导体（MOS）器件，其本身是通过使用半加工的LOCOS工艺氧化多晶硅而获得的 。 本发明最为普遍地涉及一种半导体器件，它包括：第一导电类型的半导体衬底; 基板上的栅极绝缘体，栅极绝缘体与衬底共用界面; 所述栅电极在所述栅绝缘体上具有第一侧和第二侧之间的第一侧，第二侧和中间区; 在栅极电极的第一侧的衬底内的第二导电类型的源极掺杂区域和衬底内的第二导电类型的漏极掺杂区域到栅电极的第二侧， 与栅电极对准; 以及在栅电极下方的衬底内的第一导电类型的沟道掺杂区域，沟道掺杂区域具有峰值掺杂浓度分布，使得栅极电极的中间区域附近的峰值掺杂剂浓度进一步低于栅绝缘体衬底 界面比在栅电极的第一侧下的峰值掺杂浓度或栅电极的第二侧下的峰值掺杂剂浓度。

公开(公告)号：US6130153A

公开(公告)日：2000-10-10

申请号：US166185

申请日：1998-10-05

申请人： Jae-Hee Ha

发明人： Jae-Hee Ha

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L21/76838

摘要： An interconnection fabricating method for a semiconductor device includes the steps of forming an interconnection layer on a semiconductor substrate, forming a first photoresist layer on the interconnection layer, forming an insulation layer on the first photoresist layer, forming a second photoresist layer pattern on the insulation layer, sequentially etching the insulation layer and the first photoresist layer to obtain an insulation layer pattern and a first photoresist layer pattern, and removing the second photoresist layer pattern, removing the insulation layer pattern using dry etching, and forming an interconnection layer pattern by selectively etching the interconnection layer.

摘要翻译： 一种用于半导体器件的互连制造方法包括以下步骤：在半导体衬底上形成互连层，在互连层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成绝缘层，在绝缘层上形成第二光致抗蚀剂层图案 层，依次蚀刻绝缘层和第一光致抗蚀剂层以获得绝缘层图案和第一光致抗蚀剂层图案，并且去除第二光致抗蚀剂层图案，使用干蚀刻去除绝缘层图案，并且通过选择性地形成互连层图案 蚀刻互连层。

公开(公告)号：US6127668A

公开(公告)日：2000-10-03

申请号：US1941

申请日：1997-12-31

申请人： Euy Hyeon Baek

发明人： Euy Hyeon Baek

IPC分类号： H01L27/14 ,  H01L27/146 ,  H01L27/148 ,  H01L31/0232 ,  H04N5/335 ,  H04N5/359 ,  H04N5/369 ,  H04N5/3722 ,  H04N5/3728 ,  H01J40/14

CPC分类号： H01L27/14627 ,  H01L27/14806 ,  H01L27/14818 ,  H01L27/14831 ,  H01L31/0232

摘要： A solid state image pickup device including implanting impurity ions into a planarizing layer and/or a microlens layer thereon for changing a refractive index thereof, and method for fabricating such a device. The planarizing layer and the microlens layer are formed over components of the solid state image pickup device including a plurality of photoelectric conversion regions and charge coupled device (CCD) regions, each charge coupled device transferring an image charge generated in the photoelectric conversion regions in one direction.

摘要翻译： 一种固态摄像装置，包括将杂质离子注入平坦化层和/或其上的微透镜层以改变其折射率，以及制造这种器件的方法。 平坦化层和微透镜层形成在包括多个光电转换区域和电荷耦合器件（CCD）区域的固态图像拾取器件的部件上，每个电荷耦合器件将在光电转换区域中产生的图像电荷传送到一个 方向。

公开(公告)号：US6121834A

公开(公告)日：2000-09-19

申请号：US286435

申请日：1999-04-06

申请人： Seong Ryeol Kim

发明人： Seong Ryeol Kim

IPC分类号： H03M7/30 ,  H03F1/30 ,  H03G1/04 ,  H03G7/08 ,  H03G3/20

CPC分类号： H03G7/08 ,  H03F1/30 ,  H03G1/04

摘要： A signal compressing apparatus is disclosed, which controls output signal in case of exceeding input signal to increase transmission efficiency and obtains stable output due to temperature compensation. The signal compressing apparatus includes an amplifier for amplifying an input signal applied through an input resistor connected to an input terminal at a constant gain, and a gain controller for rectifying only a specific band signal of output signals of the amplifier between the input terminal of the amplifier and an output terminal thereof, compensating temperature of the rectified signal, and outputting a control signal to allow the gain of the amplifier to be constant.

摘要翻译： 公开了一种信号压缩装置，其在超过输入信号的情况下控制输出信号以增加传输效率并且由于温度补偿而获得稳定的输出。 信号压缩装置包括：放大器，用于放大以恒定增益连接到输入端子的输入电阻器施加的输入信号;以及增益控制器，用于仅在所述输入端子的输入端之间整流放大器的输出信号的特定频带信号 放大器及其输出端子，补偿整流信号的温度，并输出控制信号以允许放大器的增益恒定。

公开(公告)号：US6121072A

公开(公告)日：2000-09-19

申请号：US35128

申请日：1998-03-05

申请人： Woong-Lim Choi ,  Kyeong-Man Ra

发明人： Woong-Lim Choi ,  Kyeong-Man Ra

IPC分类号： H01L27/112 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115

摘要： A method of fabricating a nonvolatile memory device having a substrate, includes the steps of forming a plurality of bit lines in the substrate, forming a plurality of field oxide layers on the substrate perpendicular to the bit lines, forming a gate insulating layer on an entire surface of the substrate including the bit lines and the field oxide layers, forming a plurality of floating lines on the gate insulating layer between the bit lines, forming a dielectric layer on the entire surface of the semiconductor substrate including the floating line's and the gate insulating layer, forming a plurality of word lines between the field oxide layer perpendicular to the bit lines, forming sidewall spacer at both sides of the word lines, selectively removing the dielectric layer and the floating lines using the word lines and the sidewall spacer as masks to form a plurality of floating gates, forming a tunneling layer at both sides of the floating gates, and forming a plurality of program lines between the bit lines.

摘要翻译： 一种制造具有衬底的非易失性存储器件的方法，包括在衬底中形成多个位线的步骤，在垂直于位线的衬底上形成多个场氧化物层，在整个衬底上形成栅极绝缘层 包括位线和场氧化物层的衬底的表面，在位线之间的栅极绝缘层上形成多条浮动线，在包括浮动线的半导体衬底和栅极绝缘层的整个表面上形成介电层 层，在垂直于位线的场氧化层之间形成多个字线，在字线的两侧形成侧壁间隔物，使用字线和侧壁间隔件作为掩模选择性地去除电介质层和浮动线， 形成多个浮动栅极，在浮动栅极的两侧形成隧道层，并形成多个程序 在位线之间。