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公开(公告)号：US11637047B2
公开(公告)日：2023-04-25
申请号：US17875443
申请日：2022-07-28
发明人： Pu-Ju Lin , Kai-Ming Yang , Cheng-Ta Ko
IPC分类号： H01L21/56 , H01L23/31 , H01L23/522 , H01L23/00 , H01L21/78
摘要： A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.
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公开(公告)号：US11579178B1
公开(公告)日：2023-02-14
申请号：US17647012
申请日：2022-01-04
IPC分类号： G01R29/08
摘要： An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.
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公开(公告)号：US20220408547A1
公开(公告)日：2022-12-22
申请号：US17896053
申请日：2022-08-25
发明人： Yu-Shen Chen
IPC分类号： H05K1/02 , H01L23/498 , H01L21/48 , H01L23/367
摘要： A method for manufacturing an embedded component structure includes providing a circuit board having a through hole and a heat dissipation layer; disposing a chip in the through hole; forming a dielectric layer on a first surface and a second surface of the circuit board to seal the chip and cover a lower surface of the heat dissipation layer; removing a first part of the dielectric layer to form a first opening from which a upper surface of the heat dissipation layer is exposed and a second opening from which the lower surface of the heat dissipation layer is exposed; and forming a thermal conductive material layer in the first and the second opening to form a heat dissipation element surrounding the chip. The upper surface of the heat dissipation layer is exposed from the through hole. The chip, the circuit board, and the heat dissipation element are electrically connected.
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公开(公告)号：US11523505B2
公开(公告)日：2022-12-06
申请号：US17406115
申请日：2021-08-19
发明人： Yu-Shen Chen , I-Ta Tsai , Chien-Chih Chen
摘要： An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.
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公开(公告)号：US20220344248A1
公开(公告)日：2022-10-27
申请号：US17235944
申请日：2021-04-21
发明人： John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Kai-Ming Yang , Chi-Hai Kuo , Chia-Yu Peng , Tzyy-Jang Tseng
IPC分类号： H01L23/498 , H01L25/065 , H01L23/538 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
摘要： A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
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公开(公告)号：US11483925B2
公开(公告)日：2022-10-25
申请号：US17185216
申请日：2021-02-25
发明人： Chun Hung Kuo , Kuo Ching Chen
摘要： A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.
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公开(公告)号：US11424216B2
公开(公告)日：2022-08-23
申请号：US17030380
申请日：2020-09-24
发明人： Chia-Fu Hsu , Kai-Ming Yang , Pu-Ju Lin , Cheng-Ta Ko
摘要： A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.
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公开(公告)号：US11419222B2
公开(公告)日：2022-08-16
申请号：US16784219
申请日：2020-02-06
发明人： Hsin-Chi Hu
摘要： A method of manufacturing a circuit board includes: providing a substrate including a bottom layer and a resin layer over the bottom layer, the resin layer including a first surface in contact with the bottom layer and a second surface opposite to the first surface; forming a plurality of vias through the resin layer; depositing a first metal layer in the vias, the first metal layer filling a portion of each of the vias; depositing a second metal layer over the first metal layer and in the vias; forming a patterned metal layer over the second metal layer and extending from each of the vias to a position over the second surface; separating the bottom layer and the resin layer; and removing a portion of the resin layer from the first surface, so that the first metal layer protrudes from the resin layer.
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公开(公告)号：US11410933B2
公开(公告)日：2022-08-09
申请号：US17314055
申请日：2021-05-07
发明人： John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Tzyy-Jang Tseng , Ra-Min Tain , Kai-Ming Yang
IPC分类号： H01L21/00 , H01L23/538 , H01L25/065 , H01L23/00 , H01L21/48 , H01L25/00
摘要： A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.
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公开(公告)号：US20220232702A1
公开(公告)日：2022-07-21
申请号：US17367419
申请日：2021-07-05
发明人： Yunn-Tzu Yu , Ching-Ho Hsieh , Wang-Hsiang Tsai
摘要： A circuit board structure includes a body, multiple first pads, a conductive assembly, multiple first engaging components, and multiple second engaging components. The body includes a first portion and a second portion integrally formed. A first surface of the first portion directly contacts a second surface of the second portion. A first region of the first surface protrudes from the second portion, and a second region of the second surface protrudes from the first portion. The first pads and the first engaging components are disposed on the first portion of the body and located in the first region of the first surface. The conductive assembly and the second engaging components are disposed on the second portion of the body and located in the second region of the second portion. The first pads are located between the first engaging components, and the conductive assembly is located between the second engaging components.
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