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公开(公告)号：US12218017B2
公开(公告)日：2025-02-04
申请号：US17586106
申请日：2022-01-27
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Wen Yu Lin , Kai-Ming Yang , Pu-Ju Lin
Abstract: The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.
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公开(公告)号：US20250040051A1
公开(公告)日：2025-01-30
申请号：US18236280
申请日：2023-08-21
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Chun Hung KUO , Kuo-Ching CHEN , Yu-Cheng HUANG , Yu-Hua CHEN
Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.
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公开(公告)号：US20240414850A1
公开(公告)日：2024-12-12
申请号：US18404845
申请日：2024-01-04
Applicant: Unimicron Technology Corp.
Inventor： Chin-Sheng Wang , Ra-Min Tain , Chih-Kai Chan , Shih-Lian Cheng
Abstract: A circuit board structure includes a core layer, at least one electroplating metal layer, at least one dielectric layer and at least one conductive metal layer. The core layer includes at least one dielectric portion and at least one metal portion. The electroplating metal layer is disposed on at least one of a first surface and a second surface of the core layer, exposing a portion of at least one of the first surface and the second surface and at least connecting the at least one metal part. The dielectric layer is disposed on at least one of the first surface and the second surface and on the electroplating metal layer. The dielectric layer has at least one opening exposing a portion of the electroplating metal layer. The conductive metal layer is disposed in the opening of the dielectric layer and is correspondingly connected to the electroplating metal layer.
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公开(公告)号：US20240397621A1
公开(公告)日：2024-11-28
申请号：US18345440
申请日：2023-06-30
Applicant: UNIMICRON TECHNOLOGY CORP. , National Taiwan University
Inventor： Chin-Hsun WANG , Ruey-Beei WU , Chun-Jui HUANG , Wei-Yu LIAO , Ching-Sheng CHEN , Chi-Min CHANG
Abstract: A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.
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公开(公告)号：US12133323B2
公开(公告)日：2024-10-29
申请号：US18058381
申请日：2022-11-23
Applicant: UNIMICRON TECHNOLOGY CORP. , National Taiwan University
Inventor： Chin-Hsun Wang , Ruey-Beei Wu , Ching-Sheng Chen , Chun-Jui Huang , Wei-Yu Liao , Chi-Min Chang
CPC classification number: H05K1/0242 , H01P3/08
Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
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Patent Agency Ranking
公开(公告)号：US20240357748A1
公开(公告)日：2024-10-24
申请号：US18317756
申请日：2023-05-15
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Jeng-Ting LI , Chi-Hai KUO , Cheng-Ta KO , Pu-Ju LIN
CPC classification number: H05K3/002 , H05K1/0306 , H05K2203/107
Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.
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公开(公告)号：US12022612B2
公开(公告)日：2024-06-25
申请号：US17662224
申请日：2022-05-05
Applicant: Unimicron Technology Corp.
Inventor： Chun-Hung Kuo
CPC classification number: H05K1/111 , H05K3/4644 , H05K1/025
Abstract: The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.
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公开(公告)号：US11991824B2
公开(公告)日：2024-05-21
申请号：US17448893
申请日：2021-09-26
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Shao-Chien Lee , Ming-Ru Chen , Cheng-Chung Lo
IPC: H05K1/02 , G02F1/1333 , G02F1/1368 , H05K1/03 , H05K1/11 , H05K3/00 , H10K59/12 , H10K59/123 , H10K59/124 , H10K59/131
CPC classification number: H05K1/115 , H05K1/0306 , H05K3/0067 , H05K3/0094
Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.
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公开(公告)号：US11955587B2
公开(公告)日：2024-04-09
申请号：US17227391
申请日：2021-04-12
Applicant: Unimicron Technology Corp.
Inventor： Jeng-Ting Li , Chi-Hai Kuo , Cheng-Ta Ko , Pu-Ju Lin
CPC classification number: H01L33/62 , H01L27/156 , H01L33/005 , H01L2933/0066
Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
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公开(公告)号：US11937366B2
公开(公告)日：2024-03-19
申请号：US17701964
申请日：2022-03-23
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzu Hsuan Wang , Yu Cheng Lin
IPC: H05K1/02
CPC classification number: H05K1/024 , H05K1/0242 , H05K1/0251 , H05K1/0298 , H05K2201/0187 , H05K2201/0195
Abstract: A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.
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