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18 条记录 (耗时 0.017 秒)

    Self-aligned symmetric intrinsic device
    2.
    发明授权
    Self-aligned symmetric intrinsic device 有权
    自对准对称固有装置

    公开(公告)号：US06242794B1

    公开(公告)日：2001-06-05

    申请号：US09311149

    申请日：1999-05-13

    申请人： Paul Enquist

    发明人： Paul Enquist

    IPC分类号： H01L27082

    CPC分类号： H01L29/7722 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

    摘要： A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

    摘要翻译： 一种半导体器件及其制造方法。 发射极区域与基极区域对称地形成为自对中和自对准。 使用前端处理技术，集电极形成为与基极区域和发射极区域对称自对准。 可以使用背面处理技术使收集器区域进一步与基部区域自身居中。 自对准和自对中结构的对称结构实际上消除了器件中的寄生元件，显着提高器件性能。 该器件的可扩展性约为0.1微米。 该方法还提供对称设备的商业制造所需的设备特性的可再现性和可重复性。

    Self aligned symmetric intrinsic process and device
    6.
    发明授权
    Self aligned symmetric intrinsic process and device 有权
    自对准对称固有过程和装置

    公开(公告)号：US06756281B2

    公开(公告)日：2004-06-29

    申请号：US10096742

    申请日：2002-03-14

    申请人： Paul Enquist

    发明人： Paul Enquist

    IPC分类号： H01L21331

    CPC分类号： H01L29/7722 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

    摘要： A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

    摘要翻译： 一种半导体器件及其制造方法。 发射极区域与基极区域对称地形成为自对中和自对准。 使用前端处理技术，集电极形成为与基极区域和发射极区域对称自对准。 可以使用背面处理技术使收集器区域进一步与基部区域自身居中。 自对准和自对中结构的对称结构实际上消除了器件中的寄生元件，显着提高器件性能。 该器件的可扩展性约为0.1微米。 该方法还提供对称设备的商业制造所需的设备特性的可再现性和可重复性。

    Self aligned symmetric intrinsic process and device
    7.
    发明授权
    Self aligned symmetric intrinsic process and device 有权

    公开(公告)号：US06740909B2

    公开(公告)日：2004-05-25

    申请号：US09822335

    申请日：2001-04-02

    申请人： Paul Enquist

    发明人： Paul Enquist

    IPC分类号： H01L310328

    CPC分类号： H01L29/7722 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

    摘要： A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

    Wafer scale die handling
    10.
    发明申请
    Wafer scale die handling 有权
    晶片刻度处理

    公开(公告)号：US20050194668A1

    公开(公告)日：2005-09-08

    申请号：US10792757

    申请日：2004-03-05

    申请人： Paul Enquist ,  Gaius Fountain ,  Carl Petteway

    发明人： Paul Enquist ,  Gaius Fountain ,  Carl Petteway

    IPC分类号： H01L23/495

    CPC分类号： H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00

    摘要： A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

    摘要翻译： 一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。 该元件与半导体晶片处理设备和/或半导体晶片处理兼容。 优选地，构件容纳来自半导体晶片的至少大部分管芯。 此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将 放置在半导体封装中以形成集成电路。 提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将 放置在半导体封装中以形成集成电路。