公开(公告)号：US12131943B2

公开(公告)日：2024-10-29

申请号：US18359412

申请日：2023-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sai-Hooi Yeong ,  Yen-Chieh Huang

IPC分类号： H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.

公开(公告)号：US20240321890A1

公开(公告)日：2024-09-26

申请号：US18673632

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Te-Hsin Chiu ,  Kam-Tou Sio ,  Jiann-Tyng Tzeng

IPC分类号： H01L27/092 ,  H01L21/764 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5286 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

公开(公告)号：US12100625B2

公开(公告)日：2024-09-24

申请号：US18358708

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L21/8234

CPC分类号： H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886

摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US12100617B2

公开(公告)日：2024-09-24

申请号：US18134036

申请日：2023-04-13

申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Janbo Zhang ,  Chao-Wei Lin ,  Chia-Yi Chu ,  Yu-Cheng Tung ,  Ken-Li Chen ,  Tsung-Wen Chen

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/764 ,  H01L21/768 ,  H01L23/532 ,  H10B12/00

CPC分类号： H01L21/7682 ,  H01L21/0217 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5329 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

摘要： A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

公开(公告)号：US12094761B2

公开(公告)日：2024-09-17

申请号：US18342855

申请日：2023-06-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC分类号： H01L21/82 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

摘要： An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US12080758B2

公开(公告)日：2024-09-03

申请号：US17454871

申请日：2021-11-15

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Weichao Zhang

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/764 ,  H10B12/00

CPC分类号： H01L29/0649 ,  H01L21/0228 ,  H01L21/3212 ,  H01L21/764 ,  H10B12/30 ,  H10B12/488

摘要： The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, the substrate includes active regions and isolation regions, each of the isolation regions includes a first trench and an isolation layer formed in the first trench; removing part of the isolation layer to form first grooves; forming a first mask layer, the first mask layer covers upper surfaces of the active regions and fills the first grooves; planarizing the first mask layer, such that an upper surface of a portion of the first mask layer located above the active regions is flush with an upper surface of a portion of the first mask layer located above the isolation regions; removing part of the first mask layer, part of the isolation layer, and part of the substrate, to form second trenches and third trenches.

公开(公告)号：US20240282637A1

公开(公告)日：2024-08-22

申请号：US18613151

申请日：2024-03-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC分类号： H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

公开(公告)号：US12046682B2

公开(公告)日：2024-07-23

申请号：US17689322

申请日：2022-03-08

申请人： Samsung Electronics Co., Ltd.

发明人： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

摘要： An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC分类号： H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

摘要： The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US12020989B2

公开(公告)日：2024-06-25

申请号：US17815519

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Keng-Yao Chen ,  Chang-Yun Chang ,  Ming-Chang Wen

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L21/02

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823437 ,  H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228

摘要： The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.