公开(公告)号：US12113016B2

公开(公告)日：2024-10-08

申请号：US18242460

申请日：2023-09-05

申请人： ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

发明人： Prabal Upadhyaya

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L23/525 ,  H01L23/62 ,  H01L27/088 ,  H02M3/158

CPC分类号： H01L23/5256 ,  H01L23/31 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/50 ,  H01L23/62 ,  H01L27/088 ,  H02M3/1582

摘要： A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

公开(公告)号：US12107039B2

公开(公告)日：2024-10-01

申请号：US17207223

申请日：2021-03-19

申请人： CREE FAYETTEVILLE, INC.

发明人： Zach Cole ,  Steven Ericksen

IPC分类号： H01L23/50 ,  H01L23/528 ,  H05K5/00

CPC分类号： H01L23/50 ,  H01L23/5286

摘要： A power component configured to improve partial discharge performance includes at least one terminal that includes a first planar surface, a second planar surface opposite the first planar surface, and a curved surface extending from the first planar surface to the second planar surface. The power component may include at least one of the following: a power module or a bus bar.

公开(公告)号：US20240321802A1

公开(公告)日：2024-09-26

申请号：US18187180

申请日：2023-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： JUNYAN TANG ,  SUNGJUN CHUN ,  DANIEL MARK DREPS ,  WIREN DALE BECKER ,  JOSE A HEJASE ,  PAVEL ROY PALADHI ,  NAM HUU PHAM

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L24/20 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/45 ,  H01L24/85 ,  H01L2924/1432

摘要： An integrated circuit and a cable interconnect interface are disposed on a substrate and in communication with one another. The cable interconnect interface includes a first plurality of connector pads arranged in a first column and a second plurality of connector pads arranged in a second column. A radio frequency absorption layer is disposed on one or more of the first plurality of connector pads and the second plurality of connector pads. The first plurality of connector pads includes a first group of transmission connector pads and a first group of receiving connector pads. The second plurality of connector pads includes a second group of transmission connector pads and a second group of receiving connector pads. The first group of transmission connector pads is opposite the second group of transmission connector pads, and the first group of receiving connector pads is opposite the second group of receiving connector pads.

公开(公告)号：US20240297113A1

公开(公告)日：2024-09-05

申请号：US18661657

申请日：2024-05-12

申请人： BYD SEMICONDUCTOR COMPANY LIMITED

发明人： Yuqi ZHOU ,  Chunjiang LIU ,  Jianli ZHANG

IPC分类号： H01L23/50 ,  H01L23/00 ,  H01L23/367 ,  H01L23/495 ,  H01L25/065

CPC分类号： H01L23/50 ,  H01L23/3675 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/182 ,  H01L2924/30107

摘要： A semiconductor power module, a motor controller, and a vehicle are disclosed. The semiconductor power module includes: a substrate; a first conductive region, a second conductive region, a third conductive region and a fourth conductive region that are disposed on the substrate; a first power chip, a second power chip and a third power chip. The first conductive region and the second conductive region extend along the first direction of the substrate and are arranged along the second direction of the substrate, the third conductive region and the fourth conductive region are located between the first conductive region and the second conductive region and are arranged along the first direction. The first conductive region, the second conductive region and the third conductive region are configured to transmit a direct current signal, and the fourth conductive region is configured to transmit an alternating current signal.

公开(公告)号：US20240297112A1

公开(公告)日：2024-09-05

申请号：US18498188

申请日：2023-10-31

申请人： Texas Instruments Incorporated

发明人： Sylvester Ankamah-Kusi ,  Rajen Murugan ,  Harshpreet Bakshi ,  Vivek Sridharan ,  Ruben Rolda

IPC分类号： H01L23/50 ,  H01C1/14 ,  H01C7/00 ,  H01G4/012 ,  H01G4/33 ,  H01L23/552 ,  H01L25/18 ,  H01L27/01

CPC分类号： H01L23/50 ,  H01C1/14 ,  H01C7/003 ,  H01G4/012 ,  H01G4/33 ,  H01L23/552 ,  H01L25/18 ,  H01L27/01

摘要： A passive component module includes opposite first and second sides, a base extending to the second side, and a redistribution layer structure extending between the base and the first side, the redistribution layer structure including: a passive electronic component with a first component terminal and a second component terminal; a conductive metal trace that forms at least a portion of the passive electronic component; a dielectric layer abutting a portion of the conductive metal trace; a first terminal exposed along the first side and electrically coupled to the first component terminal; and a second terminal spaced apart from the first terminal and exposed along the first side, the second terminal electrically coupled to the second component terminal.

公开(公告)号：US12080630B2

公开(公告)日：2024-09-03

申请号：US18534433

申请日：2023-12-08

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

CPC分类号： H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L27/0623 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H10B63/30 ,  H10B63/845

摘要： A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.

公开(公告)号：US12074069B2

公开(公告)日：2024-08-27

申请号：US17831108

申请日：2022-06-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Li-Chung Hsu ,  Sung-Yen Yeh ,  Yung-Chen Chien ,  Jung-Chan Yang ,  Tzu-Ying Lin

IPC分类号： H01L23/535 ,  H01L21/48 ,  H01L21/822 ,  H01L23/50

CPC分类号： H01L21/8221 ,  H01L21/4828 ,  H01L23/50 ,  H01L23/535

摘要： A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

公开(公告)号：US12068288B2

公开(公告)日：2024-08-20

申请号：US18179013

申请日：2023-03-06

申请人： SOCIONEXT INC.

发明人： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L27/088

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

摘要： A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US12067337B2

公开(公告)日：2024-08-20

申请号：US17377635

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC分类号： G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  G06F113/04 ,  G06F119/06

CPC分类号： G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  G06F2113/04 ,  G06F2119/06

摘要： Power grid of an integrated circuit (IC) is provided. A plurality of first power lines are formed in a first metal layer. A plurality of second power lines are formed in the first metal layer and parallel to the first power lines, and the first and second power lines are interlaced in the first metal layer. A plurality of third power lines formed in a second metal layer, and the third power lines are perpendicular to the first power lines. A plurality of fourth power lines are formed in the second metal layer and parallel to the third power lines, and the third and fourth power lines are interlaced in the second metal layer. Distances from each of the third power lines to two adjacent fourth power lines are different, and distances from each of the fourth power lines to two adjacent third power lines are the same.

公开(公告)号：US12057385B2

公开(公告)日：2024-08-06

申请号：US18360265

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L23/50 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L23/50 ,  H01L27/0886 ,  H01L29/785

摘要： Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.