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公开(公告)号：US11528029B2
公开(公告)日：2022-12-13
申请号：US16024242
申请日：2018-06-29
申请人： Intel Corporation
IPC分类号： H03L7/07 , H03L7/087 , H03L7/093 , G06F1/12 , H01L25/065 , H01L23/538 , H03L7/099 , H03L7/06 , H03L7/22
摘要： An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.
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公开(公告)号：US11329657B2
公开(公告)日：2022-05-10
申请号：US16778612
申请日：2020-01-31
发明人： Mario Motz , Veikko Summa
摘要： An integrated circuit has an oscillator circuit having an on-chip oscillator, a digital phase locked loop and a sensor. A frequency of an output signal from the oscillator circuit is adjustable. The digital phase locked loop receives the output signal from the oscillator circuit at an input and a synchronization signal based on an output signal from an external precision oscillator in the form of a crystal oscillator or MEMS oscillator at an external interface and generates a control signal in order to synchronize the frequency of the oscillator circuit with the frequency of the external crystal oscillator. The sensor is designed to measure at least one environmental parameter, wherein the digital phase locked loop is designed to take into account the at least one measured environmental parameter when generating the control signal.
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公开(公告)号：US11181616B2
公开(公告)日：2021-11-23
申请号：US17033577
申请日：2020-09-25
发明人： David C. Vacanti , Marc M. Pos
IPC分类号： G01S7/41 , G01S13/93 , G01S7/35 , G01S7/292 , G01S7/282 , H03L7/099 , H03L7/22 , G01S7/03 , G01S13/91
摘要： In some examples, a radar system includes first direct digital synthesizer (DDS) circuitry and first phase-locked loop (PLL) circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry. In some examples, the radar system further includes transmitter circuitry configured to generate a radar signal based on the first sinusoidal signal. In some examples, the radar system also includes one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal. In some examples, the radar system includes second DDS circuitry, second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, and receiver circuitry configured to process the return signal based on the second sinusoidal signal.
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公开(公告)号：US09571109B2
公开(公告)日：2017-02-14
申请号：US14671259
申请日：2015-03-27
IPC分类号： H03L7/06 , H03L7/085 , H03L7/099 , H03L3/00 , H03B5/06 , H03L7/18 , H03L7/22 , H03L7/14 , H03L7/10
CPC分类号： H03L7/085 , H03B5/06 , H03K23/42 , H03L3/00 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L7/22 , H03L7/23
摘要： A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.
摘要翻译： 用于防止锁相环（PLL）电路中的压控振荡器（VCO）失控的反馈模块可以包括第一，第二和第三输入端，以从PLL电路接收第一输出信号，参考信号和 第一控制信号。 反馈模块还可以包括用于产生第二控制信号的反馈电路，第二控制信号耦合到PLL电路的输入端，其中反馈电路通过比较第一输出信号的周期数来产生第二控制信号 到第一阈值，以及参考信号的周期数到第二阈值。
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公开(公告)号：US09548751B2
公开(公告)日：2017-01-17
申请号：US14821481
申请日：2015-08-07
申请人： NXP B.V.
发明人： Jean-Robert Tourret
摘要： An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.
摘要翻译： 一种用于提供相位相干信号的RF电路，包括RF电路的RF加热装置和用于在RF电路中提供相位相干信号的方法。 RF电路具有包括N分相锁相环的第一频率合成器和包括整数N个锁相环的第二频率合成器。 第一频率合成器的输出经由用于将来自第一频率合成器的同步信号分配给第二频率合成器的同步信号分频器连接到第二频率合成器的整数N锁相环的相位频率检测器。 第二频率合成器的整数N锁相环包括与同步信号分频器相同模数的分频器。
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公开(公告)号：US09065458B2
公开(公告)日：2015-06-23
申请号：US13641333
申请日：2011-04-11
摘要： A frequency synthesizer and oscillator are disclosed for reducing noise in processed signals. The synthesizer and oscillator comprise an array of frequency dividers adapted to receive an input signal, which is derived from a single signal source having a prescribed frequency. The synthesizer and oscillator further comprise at least one frequency multiplier coupled to at least one of the frequency dividers, such that in use, the dividers and the at least one multiplier are operable to generate a plurality of frequencies which are coherent with the prescribed frequency. A regulated power supply is also disclosed comprising a filter and first and second regulators, for reducing noise in the output voltage of the power supply.
摘要翻译： 公开了一种用于降低处理信号中的噪声的频率合成器和振荡器。 合成器和振荡器包括适于接收从具有规定频率的单个信号源导出的输入信号的分频器阵列。 合成器和振荡器还包括耦合到至少一个分频器的至少一个频率乘法器，使得在使用中，分频器和至少一个乘法器可操作以产生与规定频率相干的多个频率。 还公开了一种稳压电源，其包括滤波器和第一和第二调节器，用于降低电源的输出电压中的噪声。
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7.发明授权Semiconductor device generating internal clock signal having higher frequency than that of input clock signal 有权产生具有比输入时钟信号频率高的内部时钟信号的半导体器件公开(公告)号：US09054713B2
公开(公告)日：2015-06-09
申请号：US13959119
申请日：2013-08-05
申请人： ELPIDA MEMORY, INC.
CPC分类号： H03L7/0802 , G11C7/222 , G11C11/4076 , G11C29/12015 , G11C29/14 , H03L7/0816 , H03L7/22
摘要： Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.
摘要翻译： 这里公开了一种装置，其包括：多个延迟电路，每个延迟电路包括输入节点，输出节点，第一功率节点和第二功率节点，以及控制电路。 延迟电路与接收第一时钟信号的前导延迟电路的输入节点和最后一个延迟电路的输出节点串联耦合，产生第二时钟信号。 控制电路被耦合以接收第一和第二时钟信号，以控制在第一和第二电力线之间提供的工作电压。 延迟电路的第一功率节点共同连接到第一电力线，并且第二电力节点延迟电路共同连接到第二电力线。
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公开(公告)号：US09054677B2
公开(公告)日：2015-06-09
申请号：US14263492
申请日：2014-04-28
IPC分类号： H04B1/06 , H04B7/00 , H03J7/02 , G01S19/23 , H03J1/00 , H03J7/04 , H03L7/197 , H03L7/22 , H03L7/08 , H04B1/16
CPC分类号： H03J7/02 , G01S19/23 , H03J1/005 , H03J7/04 , H03L7/0805 , H03L7/197 , H03L7/22 , H04B1/16 , H04B1/3805 , H04W84/12
摘要： A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.
摘要翻译： 无线通信系统包括时钟模块，通信模块，接收模块和基带模块。 时钟模块被配置为生成第一个时钟参考。 通信模块被配置为响应于第一时钟参考而操作，并且独立于校正的时钟参考。 通过根据自动频率校正信号对第一时钟基准执行自动频率校正来产生校正的时钟基准。 接收器模块被配置为（i）从无线介质接收射频信号，以及（ii）响应于校正的时钟参考，基于所接收的射频信号产生基带信号。 基带模块被配置为（i）接收基带信号，以及（ii）响应于所选择的第一时钟参考和校正时钟参考中的一个，基于基带信号生成自动频率校正信号。
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公开(公告)号：US07902928B2
公开(公告)日：2011-03-08
申请号：US12028019
申请日：2008-02-08
申请人： Ping-Ying Wang
发明人： Ping-Ying Wang
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/093
摘要： A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.
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公开(公告)号：US06914464B2
公开(公告)日：2005-07-05
申请号：US10620509
申请日：2003-07-16
申请人： Minoru Maeda
发明人： Minoru Maeda
CPC分类号： H03L7/1806 , H03L7/1974 , H03L7/23
摘要： Phase-locked loop (PLL) circuits include first and second PLL stages and use fractional frequency division. In one implementation, the first stage includes a voltage-controlled oscillator (VCO) whose output is provided to both first and second fractional frequency dividers. The output of the first frequency divider is provided to a first phase comparator whose output passes through a filter so as to provide the deviation signal that controls the output frequency of the first VCO. The output of the second fractional frequency divider is received by the second PLL stage as a reference signal.
摘要翻译： 锁相环（PLL）电路包括第一和第二PLL阶段，并使用分数分频。 在一个实现中，第一级包括压控振荡器（VCO），其输出被提供给第一和第二分数分频器。 第一分频器的输出被提供给第一相位比较器，其输出通过滤波器，以便提供控制第一VCO的输出频率的偏差信号。 第二分频分频器的输出由第二PLL级作为参考信号接收。
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