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    MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE
    83.
    发明申请
    MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE 审中-公开
    记忆元件及其制造方法和半导体器件

    公开(公告)号：WO2008059940A1

    公开(公告)日：2008-05-22

    申请号：PCT/JP2007/072232

    申请日：2007-11-08

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  YOSHIZUMI, Kensuke

    Inventor： YOSHIZUMI, Kensuke

    IPC: H01L27/10 ,  H01L27/28 ,  H01L51/05

    CPC classification number: H01L27/1214 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0014 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/12 ,  H01L27/1203 ,  H01L45/145 ,  Y10S977/773

    Abstract: The memory element has a structure at least including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer is formed by a droplet discharge method using nanoparticles of a conductive material each of which is coated with an organic thin film. Specifically, a composition in which nanoparticles of a conductive material each of which is coated with an organic thin film are dispersed in a solvent is discharged (ejected) as ink droplets, and the solvent is dried to be vaporized to form the memory layer. Accordingly, a memory element can be formed simply. In addition, efficiency in the use of materials can be improved and yield is also improved, so that the memory element can be provided at low cost.

    Abstract translation: 存储元件具有至少包括第一导电层，第二导电层和设置在第一导电层和第二导电层之间的存储层的结构。 存储层通过使用导电材料的纳米颗粒的液滴喷射法形成，每个导电材料都涂覆有机薄膜。 具体而言，将涂布了有机薄膜的导电性材料的纳米粒子分散在溶剂中的组合物以墨滴的形式排出（喷射），将溶剂干燥而蒸发形成记忆层。 因此，可以简单地形成存储元件。 此外，可以提高材料使用的效率，并且提高产量，从而可以以低成本提供存储元件。

    DISTORTION-TOLERANT PROCESSING
    84.
    发明申请
    DISTORTION-TOLERANT PROCESSING 审中-公开
    失败处理

    公开(公告)号：WO2008041027A1

    公开(公告)日：2008-04-10

    申请号：PCT/GB2007/050599

    申请日：2007-10-01

    Applicant: PLASTIC LOGIC LIMITED ,  CAIN, Paul ,  HAYTON, Carl

    Inventor： CAIN, Paul ,  HAYTON, Carl

    IPC: H05K3/02 ,  H05K1/00 ,  H01L21/77 ,  H01L27/28 ,  H01L27/32 ,  H01L51/00

    CPC classification number: H01L27/283 ,  G03F7/70791 ,  H01L27/124 ,  H01L51/0018 ,  H01L51/0021 ,  H01L51/0097 ,  H01L51/0541 ,  Y02E10/549 ,  Y02P70/521

    Abstract: The present invention relates to a distortion-tolerant method of processing an integrated circuit, incorporating a flexible substrate or a substrate that is susceptible to distortion. In particular, the present invention provides a method of manufacturing an integrated circuit (IC) for driving a flexible display, comprising: depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repet it ive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment.

    Abstract translation: 本发明涉及一种加工容易产生变形的柔性基板或基板的集成电路的变形容忍方法。 特别地，本发明提供一种制造用于驱动柔性显示器的集成电路（IC）的方法，包括：在柔性基板上的第一层中沉积空间非重复特征的图案，所述空间不重复的图案 特征在基板的平面中在两个正交方向（x，y）两者中基本不规则地重复; 在所述第一层上沉积在第二层中的空间重复图案; 对准所述第二层和所述第一层以允许所述非重复特征和所述重复特征之间的电耦合，其中在沉积所述重复特征期间施加失真补偿以使得能够进行对准。

    FERROELECTRIC POLYMER MEMORY DEVICE INCLUDING POLYMER ELECTRODES AND METHOD OF FABRICATING THE SAME
    87.
    发明申请
    FERROELECTRIC POLYMER MEMORY DEVICE INCLUDING POLYMER ELECTRODES AND METHOD OF FABRICATING THE SAME 审中-公开
    包含聚合物电极的电介质聚合物存储装置及其制造方法

    公开(公告)号：WO2006036691A3

    公开(公告)日：2006-08-03

    申请号：PCT/US2005033811

    申请日：2005-09-21

    Applicant: INTEL CORP ,  ROCKFORD LEE ,  ANDIDEH EBRAHIM

    Inventor： ROCKFORD LEE ,  ANDIDEH EBRAHIM

    IPC: H01L27/28 ,  G11C11/22 ,  H01L27/115 ,  H01L51/05 ,  H01L51/30

    CPC classification number: G11C11/22 ,  B82Y10/00 ,  H01L27/11502

    Abstract: A method of fabricating a ferroelectric memory module with conducting polymer electrodes, and a ferroelectric memory module fabricated according to the method are disclosed. The ferroelectric polymer memory module includes a first set of layers including: an ILD layer (102) defining trenches therein; a first electrode layer (104) disposed in the trenches; a first conductive polymer layer (106) disposed on the first electrode layer (104); and a ferroelectric polymer layer (108) disposed on the first conductive polymer layer (106). The module further includes a second set of layers including: an ILD layer (114) defining trenches therein; a second conductive polymer layer (112) disposed in the trenches of the ILD layer (114) of the second set of layers; and a second electrode layer (116) disposed on the second conductive polymer layer (112). The first conductive polymer layer (106) and the second conductive polymer layer (112) cover the electrode layers (104, 116) to provide a reaction and/or diffusion barrier between the electrode layers (104, 116) and the ferroelectric polymer layer (108).

    Abstract translation: 公开了一种制造具有导电聚合物电极的铁电存储器模块的方法和根据该方法制造的铁电存储器模块。 铁电聚合物存储器模块包括第一组层，其包括：限定其中的沟槽的ILD层; 布置在所述沟槽中的第一电极层（104） 设置在第一电极层（104）上的第一导电聚合物层（106）; 和设置在第一导电聚合物层（106）上的铁电聚合物层（108）。 该模块还包括第二组层，其包括：限定其中的沟槽的ILD层（114） 设置在第二组层的ILD层（114）的沟槽中的第二导电聚合物层（112） 和设置在第二导电聚合物层（112）上的第二电极层（116）。 第一导电聚合物层（106）和第二导电聚合物层（112）覆盖电极层（104,116）以在电极层（104,116）和铁电聚合物层（104,116）之间提供反应和/或扩散阻挡层 108）。

    DUAL-GATE TRANSISTORS
    89.
    发明申请
    DUAL-GATE TRANSISTORS 审中-公开
    双门极晶体管

    公开(公告)号：WO2005098959A3

    公开(公告)日：2006-04-27

    申请号：PCT/GB2005001309

    申请日：2005-04-05

    Applicant: UNIV CAMBRIDGE TECH ,  CHUA LAY-LAY ,  HO PETER KIAN HOON ,  FRIEND RICHARD HENRY

    Inventor： CHUA LAY-LAY ,  HO PETER KIAN HOON ,  FRIEND RICHARD HENRY

    IPC: H01L51/10 ,  H01L27/28 ,  H01L29/00

    CPC classification number: H01L51/0508 ,  H01L27/283 ,  H01L51/0512 ,  H01L51/0554

    Abstract: A field Effect transistor device comprising: a source electrode (13 or 14); a drain electrode (13 or 14); a semiconductive region comprising an organic semiconductor material and defining a channel (12) of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode (10 or 16) and a first dielectric region (11 or 15) located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode (10 or 16) and a second dielectric region (11 or 15) located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode.

    Abstract translation: 场效应晶体管器件，包括：源电极（13或14）; 漏电极（13或14）; 半导体区域，包括有机半导体材料并且限定在所述源电极和所述漏电极之间的所述器件的沟道（12）; 第一栅极结构，包括位于第一栅极电极和半导体区域之间的第一栅电极（10或16）和第一介电区域（11或15） 以及第二栅极结构，包括位于所述第二栅电极和所述半导体区之间的第二栅电极（10或16）和第二电介质区（11或15） 由此沟道中的半导体区域的电导可以受单独施加的电位或第一栅极电极和第二栅极电极的影响。

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