公开(公告)号：WO2016096947A2

公开(公告)日：2016-06-23

申请号：PCT/EP2015079933

申请日：2015-12-16

Applicant: AUSTRIA TECH & SYSTEM TECH

Inventor： STAHR HANNES

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H05K3/04 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24

CPC classification number: H01L23/5389 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/08235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H05K1/0366 ,  H05K1/09 ,  H05K1/115 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0032 ,  H05K3/027 ,  H05K3/045 ,  H05K3/107 ,  H05K3/181 ,  H05K3/184 ,  H05K3/188 ,  H05K3/242 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2203/107 ,  H05K2203/1469

Abstract: A component carrier (100) for carrying electronic components (104), wherein the component carrier (100) comprises an at least partially electrically insulating core (102), at least one electronic component (104) embedded in the core (102), and a coupling structure (106, 202) with at least one electrically conductive through-connection (108) extending at least partially therethrough and having a component contacting end (112) and a wiring contacting end (114), wherein the at least one electronic component (104) is electrically contacted directly to the component contacting end (112), wherein at least an exterior surface portion of the coupling structure (106, 202) has homogeneous ablation properties and is patterned so as to have surface recesses filled with an electrically conductive wiring structure (110), and wherein the wiring contacting end (114) is electrically contacted directly to the wiring structure (110).

Abstract translation: 一种用于承载电子部件（104）的部件载体（100），其中所述部件载体（100）包括至少部分电绝缘的芯（102），嵌入在所述芯（102）中的至少一个电子部件（104），以及 具有至少一个至少部分地穿过其延伸并且具有部件接触端（112）和接线端（114）的至少一个导电贯穿连接（108）的耦合结构（106,202），其中所述至少一个电子部件 （104）直接与所述部件接触端（112）电接触，其中所述耦合结构（106,202）的至少外表面部分具有均匀的消融性能并且被图案化以具有填充有导电的表面凹槽 布线结构（110），并且其中所述布线接触端（114）与所述布线结构（110）直接电接触。

公开(公告)号：WO2014085156A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/070942

申请日：2013-11-20

Applicant: TYCO ELECTRONICS CORPORATION

Inventor： SARRAF, David Bruce

IPC: H05K3/24 ,  C23C18/16 ,  H01Q1/36 ,  H05K3/04 ,  H05K1/16

CPC classification number: H05K3/02 ,  C23C18/1653 ,  C25D5/02 ,  C25D5/48 ,  C25D7/00 ,  C25D17/005 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q7/00 ,  H05K1/0296 ,  H05K1/16 ,  H05K3/048 ,  H05K3/242 ,  H05K2201/10098 ,  H05K2203/0769

Abstract: An electrical component (100) including a substrate (102) having a circuit area (124) and a sacrificial area (126). A lift-off layer (130) is deposited on the substrate in the sacrificial area. A seed layer is deposited on the substrate in the circuit area and on the lift-off layer in the sacrificial area. A plating layer (134) is electrodeposited on the seed layer. The plating layer forms a circuit (104) in the circuit area. The plating layer forms plating electrodes (120) in the sacrificial area. The lift-off layer is removable from the substrate. The seed layer and the plating layer on the lift-off layer are removed with the lift-off layer when the lift-off layer is removed from the substrate, leaving the circuit on the substrate.

Abstract translation: 一种电子部件（100），包括具有电路区域（124）和牺牲区域（126）的基板（102）。 剥离层（130）沉积在牺牲区域的基底上。 在电路区域和牺牲区域的剥离层上的基底上沉积种子层。 电镀层（134）电沉积在种子层上。 电镀层在电路区域中形成电路（104）。 电镀层在牺牲区域中形成电镀电极（120）。 剥离层可从衬底移除。 当剥离层从衬底上移除时，剥离层上的种子层和镀层被剥离层去除，从而将电路留在衬底上。

公开(公告)号：WO2008154371A2

公开(公告)日：2008-12-18

申请号：PCT/US2008066100

申请日：2008-06-06

Applicant: SANDISK CORP ,  LIAO CHIH-CHIN ,  YE NING ,  YU CHEEMAN ,  CHIEN JACK CHANG ,  TAKIAR HEM

Inventor： LIAO CHIH-CHIN ,  YE NING ,  YU CHEEMAN ,  CHIEN JACK CHANG ,  TAKIAR HEM

IPC: H01L21/60

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09781 ,  H05K2203/175 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract translation: 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在用于半导体封装的衬底面板上获得额外的空间。

公开(公告)号：WO2008068163A2

公开(公告)日：2008-06-12

申请号：PCT/EP2007/062863

申请日：2007-11-27

Applicant: AXALTO S.A. ,  NEROT, Dorothée ,  FORTEL, Julien ,  THUILLARD, Sandrine ,  LAKNIN, Mourad

Inventor： NEROT, Dorothée ,  FORTEL, Julien ,  THUILLARD, Sandrine ,  LAKNIN, Mourad

IPC: G06K19/077 ,  H01L23/498 ,  H05K3/24

CPC classification number: H01L23/49855 ,  H01L23/60 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K1/0393 ,  H05K3/0097 ,  H05K3/242 ,  H05K2201/09354 ,  H05K2203/1545 ,  H01L2924/00

Abstract: La présente invention concerne un film-support de modules pour dispositif électronique, ledit film-support comportant un film longiligne bordé latéralement d'au moins une rive de bande métallisée et des motifs (5) de plages de contact (9) disposés sur le film, chaque motif correspondant à un module; Il se distingue en ce qu'une seule plage de contact (17) de chaque motif (9) est reliée à au moins une rive de bande (13, 15) par au moins une piste métallique (19, 27). L'invention concerne également un procédé de fabrication de module mettant en oeuvre ce film-support et module obtenu.

Abstract translation: 本发明涉及一种用于电子设备的模块的支撑膜，所述支撑膜包括在膜边缘上的细长膜。 横向设置至少一排金属化胶带和布置在所述膜上的接触垫（9）的图案（5），每个图案与其对应; 一个模块; 区别在于每个图案（9）的单个接触区域（17）彼此连接。 由至少一个金属轨道（19,27）形成至少一个带状边缘（13,15）。 本发明还涉及一种方法 模块制造使用这种支撑薄膜和获得的模块。

公开(公告)号：WO2006109997A1

公开(公告)日：2006-10-19

申请号：PCT/KR2006/001354

申请日：2006-04-12

Applicant: SIMM TECH CO., LTD ,  JUNG, Chang Bo ,  OH, Chun Hwan

Inventor： JUNG, Chang Bo ,  OH, Chun Hwan

IPC: H01L23/12

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/182 ,  H05K3/0044 ,  H05K3/064 ,  H05K3/28 ,  H05K2201/0166 ,  H01L2924/00

Abstract: Window manufacture method of semiconductor package type printed circuit board of the present invention comprises an imaging step to expose to outer as pressing a dry film, excepts a bond finger part is formed in both sides of bronze coated circuit board, an etching step to be formed bond finger to get rid of bronze of exposed the imaging step, a strip step to eliminate the pressed dry film after formed bond finger in the etching step, a solder regist spread step to insulate all area except bond finger and solder boland to be formed by the strip step, a nickel/gold plating to be formed nickel/gold plating layer to do electroplating on exposed bond finger and solder boland in the solder regist spread step.

Abstract translation: 本发明的半导体封装型印刷电路板的窗口制造方法除了在青铜电路板的两面形成接合指部以外，还具有将外部作为按压干膜而曝光的成像步骤，要形成的蚀刻步骤 粘结手指以消除暴露成像步骤的青铜，在蚀刻步骤中形成粘结指状物之后消除压制干膜的剥离步骤，焊料注射扩散步骤以使除粘结指和焊料块之外的所有区域绝缘由 条形步骤，镍/金电镀形成镍/镀金层，以在焊料注册扩展步骤中暴露的焊接指状物和焊料块进行电镀。

公开(公告)号：WO2005051060A1

公开(公告)日：2005-06-02

申请号：PCT/KR2004/002995

申请日：2004-11-19

Applicant: HUH, Sam-Man

Inventor： HUH, Sam-Man

IPC: H05K3/46

CPC classification number: H05K3/428 ,  H05K3/184 ,  H05K3/242 ,  H05K3/429 ,  H05K2203/0542

Abstract: A method for manufacturing a multi-layer PCB, and the PCB manufactured by the method. The method comprises an inner and outer layer circuit forming step, a multi-layer board forming step, a hole forming step, and a surface processing step. At the inner and outer layer forming step, fine circuits are formed on the inner layers and outer layers respectively. At the multi-layer board forming step, a multi-layer board is formed by bonding the inner layers and the outer layers where the fine circuits are formed. At the hole forming step, holes are formed in the formed board. At the surface processing step, an electroplating layer is formed on the inside walls of the holes and on predetermined parts using a photoresist layer. As the fine circuits are formed on the outer layers as well as the inner layers before forming the holes, finer and more reliable circuits can be formed on the outer layers as on the inner layers, and a steplike discontinuity problem of the products can be solved. Also, the productivity is improved by continuous and mass production, because the processes are divided and performed in similar group.

Abstract translation: 一种用于制造多层PCB的方法，以及通过该方法制造的PCB。 该方法包括内层和外层电路形成步骤，多层板形成步骤，孔形成步骤和表面处理步骤。 在内层和外层形成步骤中，分别在内层和外层上形成微细电路。 在多层板形成工序中，通过将形成有微细电路的内层和外层粘合而形成多层基板。 在孔形成步骤中，在所形成的板上形成孔。 在表面处理步骤中，使用光致抗蚀剂层在孔的内壁和预定部分上形成电镀层。 由于在形成孔之前在外层和内层上形成微细电路，所以可以在内层上形成更细且更可靠的电路到外层上，并且可以解决产品的阶梯状不连续性问题 。 而且，连续批​​量生产提高了生产效率，因为这些工艺是以类似的组合划分和执行的。

公开(公告)号：WO0213254A3

公开(公告)日：2003-01-03

申请号：PCT/US0123789

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： VIVARES VALERIE ,  FONTECHA EDWIN R

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/02 ,  H05K3/24 ,  H05K3/10

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/02 ,  H05K3/027 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1572 ,  H05K2203/175 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A method of electroplating circuit board substrate having a high density, multi-trace circuit pattern formed on at least one major surface of an insulative substrate, without requiring formation and at least partial removal of a large plurality of electrically conductive tie bars contacting each of the circuit traces for supplying electroplating potential/current, comprises providing the at least one major surface with a single tie bar having at least a pair of laterally extending arms in simultaneous electrical contact with an end of each trace. Portions of the tie bar extension arms are selectively removed after completion of electroplating, e.g., by laser drilling or plasma etching, to electrically separate each of the circuit traces from the tie bar. According to an embodiment of the invention, electroplating is simultaneously performed on a dual-sided substrate including electrically interconnected circuit patterns formed on opposite sides thereof. The invention enjoys particular utility in the fabrication of ball grid array (BGA) semiconductor device packages.

Abstract translation: 一种电镀电路板基板的方法，其具有形成在绝缘基板的至少一个主表面上的高密度多迹线电路图案，而不需要形成并且至少部分地去除大量多个导电连接杆 用于提供电镀电位/电流的电路迹线包括向所述至少一个主表面提供具有至少一对横向延伸的臂的单个连接杆，所述至少一个横向延伸臂与每个迹线的端部同时电接触。 连接杆延伸臂的部分例如通过激光钻孔或等离子体蚀刻在电镀完成之后被选择性地去除，以使电路迹线与连接条电气分离。 根据本发明的实施例，电镀同时在包括形成在其相对侧上的电互连电路图案的双面基板上进行。 本发明在球栅阵列（BGA）半导体器件封装的制造中具有特别的用途。

公开(公告)号：WO02013254A2

公开(公告)日：2002-02-14

申请号：PCT/US2001/023789

申请日：2001-07-26

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/02 ,  H05K3/24 ,  H05K3/10

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/498 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/02 ,  H05K3/027 ,  H05K2203/095 ,  H05K2203/107 ,  H05K2203/1572 ,  H05K2203/175 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A method of electroplating circuit board substrate having a high density, multi-trace circuit pattern formed on at least one major surface of an insulative substrate, without requiring formation and at least partial removal of a large plurality of electrically conductive tie bars contacting each of the circuit traces for supplying electroplating potential/current, comprises providing the at least one major surface with a single tie bar having at least a pair of laterally extending arms in simultaneous electrical contact with an end of each trace. Portions of the tie bar extension arms are selectively removed after completion of electroplating, e.g., by laser drilling or plasma etching, to electrically separate each of the circuit traces from the tie bar. According to an embodiment of the invention, electroplating is simultaneously performed on a dual-sided substrate including electrically interconnected circuit patterns formed on opposite sides thereof. The invention enjoys particular utility in the fabrication of ball grid array (BGA) semiconductor device packages.

Abstract translation: 一种电镀电路板基板的方法，其具有形成在绝缘基板的至少一个主表面上的高密度多迹线电路图案，而不需要形成并且至少部分地去除大量多个导电连接杆 用于提供电镀电位/电流的电路迹线包括向所述至少一个主表面提供具有至少一对横向延伸的臂的单个连接杆，所述至少一个横向延伸臂与每个迹线的端部同时电接触。 连接杆延伸臂的部分例如通过激光钻孔或等离子体蚀刻在电镀完成之后被选择性地去除，以使电路迹线与连接条电气分离。 根据本发明的实施例，电镀同时在包括形成在其相对侧上的电互连电路图案的双面基板上进行。 本发明在球栅阵列（BGA）半导体器件封装的制造中具有特别的用途。

公开(公告)号：WO01078140A2

公开(公告)日：2001-10-18

申请号：PCT/IT2001/000177

申请日：2001-04-09

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/00 ,  H05K3/06 ,  H05K3/24 ,  H05K3/28 ,  H01L23/13

CPC classification number: H01L21/4846 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/064 ,  H05K3/242 ,  H05K3/28 ,  H05K2201/09036 ,  H05K2201/0959 ,  H05K2203/0228 ,  H05K2203/0571 ,  H05K2203/162 ,  H01L2924/00

Abstract: A support (10) of the printed circuit type, also called "chip carrier", for use in the making of electronic components (50), which comprises a sheet (13) of electrically insulating material, and which has, on one side (10a), a first plurality of cells or small areas (27), each of which is provided with solder pads or mounting areas (26) for receiving and electrically connecting to a corresponding integrated electronic circuit (41), and, on the other side (10b), a second plurality of cells provided with solder pads or mounting areas (26) for the coupling of the carrier (10) with a common electronic board (48); wherein a protective layer (28) is deposited on both sides (10a, 10b) of the carrier (10) in such a way as to leave uncovered the relative mounting areas (26), and wherein the carrier (10) also has, along the outlines of the cells (27), a plurality of etchings (33) which pass through the protective layer (28) to leave uncovered the layer (13) of insulating material underneath, and which correspond to removed portions (25a) of an original conducting grid (25), used during the manufacturing process of the carrier (10) itself to deposit a thin layer of solderable material (32) on the various pads or mounting areas (26). The carrier (10), thanks to the removal of these portions (25a) of the original conducting grid (25), acquires a structure which electrically insulates the various cells (27) from one another, so that the carrier (10) may be tested advantageously together with the integrated electronic circuits (41) mounted thereon, before the stage in which the carrier (10) is divided into electronic components (50), thereby avoiding the much more costly testing of the single electronic components (50), piece by piece.

Abstract translation: 印刷电路类型的支撑体（10），也称为“芯片载体”，用于制造电子部件（50），其包括电绝缘材料的片材（13），并且其一侧 10a），第一多个单元或小区域（27），每个单元或小区域（27）设置有用于接收和电连接到相应的集成电子电路（41）的焊盘或安装区域（26），并且在另一侧 （10b），具有用于使所述载体（10）与公共电子板（48）联接的焊盘或安装区域（26）的第二多个电池单元; 其中保护层（28）沉积在所述载体（10）的两侧（10a，10b）上，以使所述相对安装区域（26）不被覆盖，并且其中所述载体（10）沿着 电池（27）的轮廓，穿过保护层（28）的多个蚀刻物（33），以覆盖下方的绝缘材料层（13），并且对应于原件的去除部分（25a） 在载体（10）本身的制造过程中使用的导电栅格（25）在不同的焊盘或安装区域（26）上沉积薄层可焊材料（32）。 由于去除原始导电栅格（25）的这些部分（25a），载体（10）获得使各种单元（27）彼此电绝缘的结构，使得载体（10）可以是 在载体（10）被分成电子部件（50）的阶段之前，与安装在其上的集成电子电路（41）一起有利地进行测试，从而避免对单个电子部件（50）进行更昂贵的测试 一块

公开(公告)号：WO1997036464A1

公开(公告)日：1997-10-02

申请号：PCT/GB1997000883

申请日：1997-03-27

Applicant: COATES BROTHERS PLC ,  THATCHER, Wrenford, John

Inventor： COATES BROTHERS PLC

IPC: H05K03/10

CPC classification number: H05K3/247 ,  H05K1/095 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/06 ,  H05K3/064 ,  H05K3/107 ,  H05K3/108 ,  H05K3/242 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2203/054

Abstract: In a process for producing a circuit board, a conductive layer (27) and a resist layer (25) are formed over a substrate (21). The resist layer (25) is patterned to define a wiring pattern. Electrolysis is used to define the wiring pattern (37), using the conductive layer (27) as the plating electrode. The conductive layer (27) is formed as a coating of a conductive ink, over the patterned resist (25).

Abstract translation: 在电路板的制造方法中，在基板（21）上形成导电层（27）和抗蚀剂层（25）。 图案化抗蚀剂层（25）以限定布线图案。 使用电解来定义布线图案（37），使用导电层（27）作为电镀电极。 导电层（27）在图案化的抗蚀剂（25）上形成为导电油墨的涂层。