公开(公告)号：EP1926355A2

公开(公告)日：2008-05-28

申请号：EP07076013.7

申请日：2007-11-21

Applicant: Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.V.

Inventor： Ostmann, Andreas ,  Seckel, Manuel ,  Löher, Thomas ,  Manessis, Dionysios ,  Patzelt, Rainer

IPC: H05K3/00 ,  H05K1/00

CPC classification number: H05K1/0271 ,  H05K1/0283 ,  H05K1/188 ,  H05K1/189 ,  H05K3/284 ,  H05K3/303 ,  H05K3/382 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09263 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/2009 ,  H05K2203/0271

Abstract: Die vorliegende Erfindung betrifft ein Verfahren zum Herstellen eines dehnbaren Schaltungsträgers, bei dem ein Ausgangsmaterial (3) für ein dehnbares Substrat auf eine elektrisch leitende Folie (1) aufgebracht wird, das eine mit der Folie (1) verbundene dehnbare Substratschicht (5) bildet, wonach die Folie (1) so strukturiert wird, dass sie eine Leiterstruktur mit mindestens einer dehnbaren Leiterbahn (7) bildet. Die Erfindung betrifft ferner einen entsprechend herstellbaren dehnbaren Schaltungsträger.

Abstract translation: 该方法涉及在可伸展基材上在导电​​箔，其形成与该箔连接的伸展底物层的涂布用基材。 箔片被在伸展导电路径规整检查做了箔形成导体结构（7）。 箔片展品的5至100微米的厚度没有形成铜或银或金。 箔片被粗糙化或氧化之前将材料施加到表面拒之门外到该层。 另一伸缩层（14）上覆盖的结构应用于gemäß到箔的结构。 因此独立claimsoft被包括用于在与可延伸到衬底电路伸展载体。

公开(公告)号：EP1884953A3

公开(公告)日：2008-04-02

申请号：EP07114348.1

申请日：1998-09-22

Applicant: Rambus, Inc.

Inventor： Perino, Donald, V. ,  Garrett, Billy, Wayne, Jr. ,  Liaw, Haw-Jyh ,  Nguyen, David ,  Nimmagadda, Srinivas ,  Gasbarro, James, A. ,  Dewitt Crisp, Richard

IPC: G11C5/00 ,  G11C5/06

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A high frequency bus system (450) which insures uniform arrival times of high fidelity signals to the devices (510), despite the use of the bus (450) on modules (420) and connectors. The high frequency bus system (450) includes a first bus segment having one or more devices (510) connected between a first and second end. The high frequency bus system (450) also includes a second bus segment which has no devices connected to it. The first end of the first segment and the second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device (510) connected to the first bus segment at substantially the same time. Conversely when two signals originate at a device (510) substantially at the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data, or control, carried by the signals.

公开(公告)号：EP1804557A1

公开(公告)日：2007-07-04

申请号：EP06026836.4

申请日：2006-12-22

Applicant: EL-ME Aktiengesellschaft

Inventor： Fischer, Markus ,  Froschermeier, Günther

IPC: H05K1/02 ,  G06F21/06

CPC classification number: G06F21/86 ,  G06F21/71 ,  H05K1/0268 ,  H05K1/0275 ,  H05K1/162 ,  H05K1/167 ,  H05K1/186 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/10151

Abstract: Ein Elektronik-Sicherheits-Modul umfaßt einen geschützten Bereich (18), in dem sicherheitsrelevante Bauteile (20) untergebracht sind. Das Elektronik-Sicherheits-Modul weist wenigstens eine erste Leiterplatte (10, 12) und eine zu dieser Leiterplatte (10, 12) benachbarte zweite Leiterplatte (10, 12) oder eine Abdeckung (38) auf. In der ersten Leiterplatte (10, 12) sind Durchkontaktierungen vorgesehen, die sich durch einen Teil der Leiterplatte (10, 12) erstrecken oder von einer ersten Seite der Leiterplatte (10, 12) durch die Leiterplatte (10, 12) hindurch zu einer der ersten Seite entgegengesetzten zweiten Seite der Leiterplatte (10,12) führen.

Abstract translation: 电子安全模块具有保护区（18），其中位于安全相关部件（20）中。 在第一电路板（10,12）中，设置电镀通孔并且延伸穿过电路板（10,12）的一部分或从电路板的第一侧通过电路板引导到相对的第二侧 的电路板（10,12）。

公开(公告)号：EP1515366A3

公开(公告)日：2007-03-21

申请号：EP04394053.5

申请日：2004-08-20

Applicant: Nortel Networks Limited

Inventor： Kwong, Herman ,  Soh, Kah Ming ,  Marcanti, Larry ,  Wyrzkowska, Aneta ,  Handforth, Martin

IPC: H01L23/498 ,  H01L23/482

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/10 ,  H01L2224/05573 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Techniques for improved contact mapping in circuit devices are disclosed. In one particular exemplary embodiment, a technique may be realized as a circuit device comprising a circuit chip having a plurality of electrical contacts positioned at a surface of the circuit chip so as to form one or more channels at the surface, the one or more channels being substantially devoid of electrical contacts such that one or more corresponding channels are formed in a chip carrier for routing electrically conductive traces from one or more of the plurality of electrical contacts on a routing layer of the chip carrier.

公开(公告)号：EP1676182A1

公开(公告)日：2006-07-05

申请号：EP04770420.0

申请日：2004-10-22

Applicant: TRINTECH LIMITED

Inventor： COLEMAN, Ronan ,  MARTIN, Michael

IPC: G06F1/00 ,  G08B13/12

CPC classification number: G06F21/86 ,  H05K1/0275 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/0999 ,  H05K2201/10151

Abstract: A secure device (1) has a circuit board (2) with various exposed components such as an LCD (4) and keys (40). A secure circuit (10) is housed within an enclosure formed between the board (2) and a cover (11). The cover (11) has, on its inside surface, a security track (23) in a dense serpentine pattern. The board (2) has a security track (52), also in a dense serpentine pattern, is an inner layer. The track (52) is linked to covered surface-level tracks (27) by vias (64). The cover's security track (23) is connected to the board's security tracks (52, 27) via a deformable pad (25) whose conductivity increases with applied compression.

公开(公告)号：EP1636838A2

公开(公告)日：2006-03-22

申请号：EP04754645.2

申请日：2004-06-03

Applicant: INTEL CORPORATION

Inventor： HESTER, Jennifer ,  LI, Yuan-Liang ,  DESMITH, Michael ,  FIGUEROA, David ,  ZHONG, Dong

IPC: H01L23/00

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

公开(公告)号：EP1557736A2

公开(公告)日：2005-07-27

申请号：EP05001196.4

申请日：2005-01-21

Applicant: PITNEY BOWES INC.

Inventor： Heitmann, Kjell A. ,  Clark, Douglas A. ,  Perreault, Paul G.

IPC: G06F1/00

CPC classification number: H01L23/576 ,  G06F21/87 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K2201/09263 ,  H05K2201/10151 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A tamper protected printed circuit board assembly including a printed circuit board and a partially enveloping tamper wrap covering the entirety of the top surface of the printed circuit board and a first portion of the bottom surface of the printed circuit board, wherein a second portion of the bottom surface of the printed circuit board is not covered by the tamper wrap is provided. The printed circuit board includes two security trace layers each having two security traces thereon, preferably in a serpentine pattern. The tamper wrap and the security traces together cover and prevent tampering with the electronic circuitry of the printed circuit board.

Abstract translation: 一种防篡改印刷电路板组件，包括印刷电路板和覆盖印刷电路板的整个顶表面的部分包封的篡改包装和印刷电路板的底表面的第一部分，其中第二部分 印刷电路板的底面未被篡改包覆覆盖。 印刷电路板包括两个安全迹线层，每个安全迹线层具有两个安全迹线，优选地以蛇形图案。 篡改包裹和安全踪迹一起覆盖并防止篡改印刷电路板的电子电路。

公开(公告)号：EP1288991A3

公开(公告)日：2004-11-24

申请号：EP02102241.3

申请日：2002-08-29

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Steinhäuser, Lothar Dr.

IPC: H01H85/44 ,  H01H85/046 ,  H01H85/46

CPC classification number: H04M3/18 ,  H01H85/046 ,  H01H85/44 ,  H01H85/463 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0293 ,  H05K1/165 ,  H05K1/18 ,  H05K2201/09263 ,  H05K2201/10181

Abstract: Zwischen den zweidrahtigen Anschluss (2) und der Kommunikationseinrichtung (3) ist jeweils ein als Überstrom-Sicherung wirkendes, durch gedruckte Leiterbahnen gebildetes Längsglied (5) eingefügt, denen ein als Überspannungsschutz wirkendes Querglied (6) nachgeschaltet ist. Die geometrische Ausgestaltung der Längsglieder (5) und die Anordnung sowie die Eigenschaften des Quergliedes (6) sind derart aufeinander abgestimmt, dass eine möglichst hohe thermische Rückkopplung vom Querglied (6) auf die Längsglieder (5) erreicht wird. Die Schutzschaltung kann kostengünstig realisiert werden und ist für hohe Anforderung an Überspannungs- und Überstromschutz geeignet.

公开(公告)号：EP1457861A1

公开(公告)日：2004-09-15

申请号：EP03005541.2

申请日：2003-03-11

Applicant: Infineon Technologies AG

Inventor： Kuzmenka, Maksim ,  Chennupati, Siva RaghuRam ,  Bacha, Abdallah ,  Muff, Simon

IPC: G06F1/10

CPC classification number: G11C7/1066 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/1506 ,  H03L7/06 ,  H03L7/07 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

Abstract: A circuit module has a circuit board (50a), multiple circuit units (20a to 52i) on the circuit board (50a) and at least one clock input (12a) on the circuit board (50a) for receiving an external clock signal. The circuit module has a first PLL unit (60) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit (62) on the circuit board (50a) for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.

Abstract translation: 电路模块具有电路板（50a），电路板（50a）上的多个电路单元（20a至52i）和电路板（50a）上的至少一个时钟输入（12a），用于接收外部时钟信号。 电路模块具有在电路板（50a）上的第一PLL单元（60），用于基于外部时钟信号向至少第一个电路单元提供内部时钟信号。 此外，电路模块在电路板（50a）上具有第二PLL单元（62），用于基于外部时钟信号向至少第二电路单元提供内部时钟信号。

公开(公告)号：EP0809260B1

公开(公告)日：2003-03-19

申请号：EP97108249.0

申请日：1997-05-21

Applicant: MOLEX INCORPORATED

Inventor： Noda, Atsuhito ,  Hoshino, Tetsuo

IPC: H01B7/08

CPC classification number: H01B7/0876 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/118 ,  H05K2201/09263 ,  H05K2201/097