公开(公告)号：EP0460822B1

公开(公告)日：1994-12-28

申请号：EP91304504.3

申请日：1991-05-20

Applicant: International Business Machines Corporation

Inventor： Frankeny, Jerome Albert ,  Frankeny, Richard Francis ,  Hermann, Karl ,  Imken, Ronald Lann

IPC: H05K3/36

CPC classification number: H05K3/429 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/0393 ,  H05K3/445 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09581 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/1438 ,  Y10T29/41

公开(公告)号：EP0460822A1

公开(公告)日：1991-12-11

申请号：EP91304504.3

申请日：1991-05-20

Applicant: International Business Machines Corporation

Inventor： Frankeny, Jerome Albert ,  Frankeny, Richard Francis ,  Hermann, Karl ,  Imken, Ronald Lann

IPC: H05K3/36

CPC classification number: H05K3/429 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/0393 ,  H05K3/445 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09581 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/1438 ,  Y10T29/41

Abstract: A multilayer, flexible substrate 64 upon which integrated circuit chips 60 can be attached is disclosed. The input/output(I/O) connections 62 from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward 68 from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.
An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material. This excised, pretested memory package, which includes both the IC chip and the flexible substrate, can then be mounted directly onto the ultimate carrier either by reflow soldering or direct bonding.

Abstract translation: 公开了可以连接集成电路芯片60的多层柔性基板64。 来自芯片的输入/输出（I / O）连接62不会从模具的侧面向外辐射，而是从底表面延伸。 由于一旦将IC芯片安装在基板上，I / O信号线将无法进行测试，因此每个I / O线从IC封装向外延伸68，从而可访问基板上的一个区域。 此外，来自每个I / O信号端口的电路同时通过其上安装有芯片的衬底层，从而提供所有I / O端口与柔性衬底的下侧的电接触。 集成电路芯片安装在该柔性基板上。 由于每个I / O线在安装后都可以访问，因此IC芯片可以在安装在其最终载体上之前进行测试。 一旦测试，将IC芯片及其安装在其上的基板从基板材料卷上切下。 包括IC芯片和柔性基板在内的这种预先测试的存储器封装可以通过回流焊接或直接接合直接安装在极限载体上。

公开(公告)号：EP0178864B1

公开(公告)日：1991-04-03

申请号：EP85307304.7

申请日：1985-10-11

Applicant: SHIKOKU CHEMICALS CORPORATION

Inventor： Tsukagoshi, Minoru ,  Nakayama, Takuo ,  Minagawa, Masahiko ,  Yoshida, Shuji

IPC: H05K3/42 ,  C23F1/02 ,  C23F11/14

CPC classification number: C23F11/149 ,  C23C22/52 ,  C23F1/02 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/0591 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/124

公开(公告)号：EP0399161A3

公开(公告)日：1991-01-16

申请号：EP90105309.0

申请日：1990-03-21

Applicant: International Business Machines Corporation

Inventor： Bregman, Mark Fielding ,  Buchwalter, Stephen Leslie ,  Hermann, Karl ,  Kovac, Caroline Ann ,  Poore, Paige Adams ,  Viehbeck, Alfred

IPC: H05K1/05 ,  H05K1/00

CPC classification number: H05K3/462 ,  H01L23/5385 ,  H01L24/00 ,  H01L2924/14 ,  H05K1/0272 ,  H05K1/056 ,  H05K1/144 ,  H05K3/321 ,  H05K3/325 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/0154 ,  H05K2201/0314 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2203/0323 ,  H05K2203/041 ,  H05K2203/1184 ,  H05K2203/1438 ,  H01L2924/00

Abstract: Structure for mounting electronic devices thereon. The structure is fabricated from a plurality of substrates (4, 6, 8, 10) each having a thermally and/or electric­ally conductive core (12) surrounded by a dielectric material (13). The substrates can be adherently placed together with the electrically conductive cores provid­ing ground and power planes or the substrates can be mounted together with connectors (42) electrically interconnecting adjacent substrates and spacing the ad­jacent substrates apart providing a space through which a fluid can flow to extract heat generated by the electronic devices mounted thereon. The conductive cores provide both power and ground planes to the structure and a means for thermally dissipating the generated heat.

公开(公告)号：EP0324352A3

公开(公告)日：1989-07-26

申请号：EP89100050.7

申请日：1989-01-03

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Hadwiger, Helmut Dipl.-Ing. ,  Schmidt, Hans-Friedrich, Dr.-Ing.

IPC: H05K3/44

CPC classification number: H05K3/445 ,  B32B15/08 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/386 ,  H05K2201/0195 ,  H05K2201/09118 ,  H05K2201/09581 ,  H05K2203/1327 ,  H05K2203/1438 ,  Y10T29/49158 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721

Abstract: 1. Verfahren zur Herstellung einer Metallkernleiterplatte. 2.1. Herstellung von zwei- bzw. dreidimensionalen Metallkern­leiterplatten beliebiger Form mit und ohne Durchkontak­tierungen. 2.2 Die Herstellung derartiger Leiterplatten kann im Spritz­gießverfahren, Spritzprägeverfahren oder in einem Preßver­fahren erfolgen. Als Leiterplattenwerkstoff kommen dabei vorzugsweise hochwärmebeständige Thermoplaste, aber auch Duroplaste zum Einsatz. Für den Kern wird ein gut wärme­leitfähiges Metall eingesetzt. Bei der Materialauswahl ist darauf zu achten, daß die Wärmeausdehnungskoeffizienten von Metallkern- und Leiterplattenwerkstoff möglichst gleich sind. Die Herstellung beinhaltet folgende Verfah­rensschritte:
ein- oder beidseitige Kaschierung der Metallplatte mit einer Kunststoffolie Einbringen des gewünschten Lochbildes mit entsprechendem Übermaß in die kaschierte Metallplatte Einlegen des derart vorbereiteten Metallkerns in das Spritzgießwerkzeug. 2.3. Automatisierungsgeräte.

公开(公告)号：EP0178864A2

公开(公告)日：1986-04-23

申请号：EP85307304.7

申请日：1985-10-11

Applicant: SHIKOKU CHEMICALS CORPORATION

Inventor： Tsukagoshi, Minoru ,  Nakayama, Takuo ,  Minagawa, Masahiko ,  Yoshida, Shuji

IPC: H05K3/42 ,  C23F1/02 ,  C23F11/14

CPC classification number: C23F11/149 ,  C23C22/52 ,  C23F1/02 ,  H05K3/0094 ,  H05K3/061 ,  H05K3/427 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/0591 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/124

Abstract: Disclosed is a process for producing a copper through-hole printed circuit board, which comprises forming a required pattern on a copper-clad laminated plate using a resist ink soluble in an alkaline aqueous solution, immersing the copper-clad laminated plate in an aqueous solution of a salt or an alkylimidazole compound represented by the following general formula
wherein R 2 represents an alkyl group having 5 to 21 carbon atoms, R 4 represents a hydrogen atom or a methyl group, and HA represents an organic or inorganic acid,
to form on the copper surface of the copper-clad laminated plate an etching resist film composed of the alkylimidazole compound, drying the resulting copper-clad laminated plate, and then treating it with an alkaline etching solution.

公开(公告)号：EP0003801B1

公开(公告)日：1982-06-09

申请号：EP79100439.3

申请日：1979-02-14

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Andreades, Sam ,  Beske, Grant Allen ,  Lott, John Walter

IPC: H05K3/10 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20 ,  G03C5/00

CPC classification number: G03F7/28 ,  G03F7/168 ,  H05K3/102 ,  H05K3/185 ,  H05K3/3468 ,  H05K3/422 ,  H05K3/426 ,  H05K2201/0347 ,  H05K2201/09581 ,  H05K2203/0278 ,  H05K2203/044 ,  H05K2203/0525 ,  H05K2203/068 ,  Y10S428/901 ,  Y10S428/936 ,  Y10T428/12049 ,  Y10T428/12097 ,  Y10T428/12104 ,  Y10T428/12361 ,  Y10T428/12396 ,  Y10T428/12569 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24893 ,  Y10T428/24909 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/252 ,  Y10T428/256 ,  Y10T428/257

公开(公告)号：EP0000673A1

公开(公告)日：1979-02-07

申请号：EP78400038.2

申请日：1978-06-28

Applicant: SOCIETE ANONYME DE TELECOMMUNICATIONS (S.A.T.)

Inventor： Lindebrings, Charles Maurice Philippe ,  Vaillagou, Pierre ,  Velte, André Jean François

IPC: H05K3/00 ,  G03F7/08

CPC classification number: H05K3/42 ,  G03F7/00 ,  G03F7/16 ,  H05K1/0366 ,  H05K3/422 ,  H05K3/427 ,  H05K2201/09581 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: Procédé de réalisation de circuits imprimés à trous métallisés à partir de supports isolants en stratifié verre-résine synthétique, dans lequel on perce les trous à métalliser dans le support isolant, on effectue un dépôt de métal conducteur par métallisation chimique dans les trous et sur les deux faces, on réalise de càblage par gravure du métal conducteur sur les deux faces après avoir déposé une réserve, puis on positionne les composants électriques dans les trous métallisés et on soude la queue des composants dans les trous respectifs pour assurer les liaisons électriques.
Immédiatement après le perçage des trous (10), on enduit le support (1) avec une résine photosensible à action positive (12) et on expose le support enduit à un rayonnement capable de détruire la résine, puis on le sèche.

公开(公告)号：EP3257335A1

公开(公告)日：2017-12-20

申请号：EP16706131.6

申请日：2016-02-06

Applicant: Häusermann GmbH

Inventor： HACKL, Johann ,  REDL, Norbert ,  HÖRTH, Stefan

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/40

CPC classification number: H05K3/429 ,  H05K1/0204 ,  H05K1/0207 ,  H05K3/4046 ,  H05K2201/09581 ,  H05K2201/0969 ,  H05K2201/09809 ,  H05K2201/10416

Abstract: Method for producing a plated-through hole between conductor tracks which are arranged at the top and at the bottom in a multilayer printed circuit board which is composed of a printed circuit board material and comprises at least one copper profile which is embedded in the composite of the multilayer printed circuit board, wherein the plated-through hole is produced by the following method steps: producing a first bore with a first bore diameter through the multilayer printed circuit board by drilling through the top and the bottom conductor track and the embedded copper profile; filling the first bore with an insulating filling material; producing a second bore coaxially in relation to the first bore with a second, smaller bore diameter than the bore diameter of the first bore; lining the bore wall of the second bore with an electrically conductive material and in this way making electrical contact with the top and bottom conductor tracks.

公开(公告)号：EP2860560A1

公开(公告)日：2015-04-15

申请号：EP13188483.5

申请日：2013-10-14

Applicant: ams AG

Inventor： Kraft, Jochen ,  Rohracher, Karl ,  Teva, Jordi

IPC: G02B6/42 ,  G02B6/43 ,  H05K1/02 ,  H05K3/46 ,  H01L23/48

CPC classification number: G02B6/4283 ,  G02B6/12002 ,  G02B6/13 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L23/481 ,  H01L23/522 ,  H01L31/16 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0939 ,  H05K2201/09518 ,  H05K2201/09581 ,  H05K2201/10174

Abstract: The semiconductor device comprises a semiconductor substrate (1) and an optical via (4) penetrating the substrate from a main surface (12) to an opposite further main surface (13). A metal via layer (5) is arranged along the optical via without closing the optical via. A contact pad (19) is arranged above the further main surface at a distance from the optical via. A through-substrate via (14) comprising a further metal via layer (15) is arranged in the substrate, the through-substrate via penetrating the substrate from the main surface to the contact pad. The further metal via layer is in electrical contact with the contact pad.

Abstract translation: 半导体器件包括半导体衬底（1）和从主表面（12）穿过衬底到相对的另一主表面（13）的光通孔（4）。 金属通孔层（5）沿着光学通孔布置，而不关闭光学通孔。 接触垫（19）布置在与光学通孔相距一定距离处的另一主表面上方。 包括另外的金属通孔层（15）的贯通基板通孔（14）被布置在基板中，穿通基板经由基板从主表面穿过基板到接触垫。 另外的金属通孔层与接触垫电接触。